David E Keating

US Patent:

45690189, Feb 4, 1986

Filed:

Nov 15, 1982

Appl. No.:

6/441967

Inventors:

Mark D. Hummel - Franklin MA
James M. Guyer - Marlboro MA
David I. Epstein - Framingham MA
David L. Keating - Holliston MA
Steven J. Wallach - Richardson TX

Assignee:

Data General Corp. - Westborough MA

International Classification:

G06F 930
G06F 1300

US Classification:

364200

Abstract:

A data processing uses instructions which may refer to operands in main memory by either physical or logical addresses. The central processor has an internal memory organized as two portions. The first portion provides a scratchpad memory function for the central processor and the second portion is responsive to logical addresses to provide corresponding physical addresses.

US Patent:

60264616, Feb 15, 2000

Filed:

Dec 9, 1998

Appl. No.:

9/208139

Inventors:

William F. Baxter - Holliston MA
Robert G. Gelinas - Westboro MA
James M. Guyer - Northboro MA
Dan R. Huck - Shrewsbury MA
Michael F. Hunt - Ashland MA
David L. Keating - Holliston MA
Jeff S. Kimmell - Chapel Hill NC
Phil J. Roux - Holliston MA
Liz M. Truebenbach - Sudbury MA
Rob P. Valentine - Auburn MA
Pat J. Weiler - Northboro MA
Joseph Cox - Middleboro MA
Barry E. Gillott - Fairport NY
Andrea Heyda - Acton MA
Rob J. Pike - Northboro MA
Tom V. Radogna - Westboro MA
Art A. Sherman - Maynard MA
Michael Sporer - Wellesley MA
Doug J. Tucker - Northboro MA
Simon N. Yeung - Waltham MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 1314

US Classification:

710244

Abstract:

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization.

US Patent:

44096550, Oct 11, 1983

Filed:

Apr 25, 1980

Appl. No.:

6/143981

Inventors:

Steven Wallach - Framingham MA
Kenneth D. Holberger - North Grafton MA
David L. Keating - Natick MA
Steven M. Staudaher - Northboro MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 900
G06F 932
G06F 934

US Classification:

364200

Abstract:

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.

US Patent:

58871462, Mar 23, 1999

Filed:

Aug 12, 1996

Appl. No.:

8/695556

Inventors:

William F. Baxter - Holliston MA
Robert G. Gelinas - Westboro MA
James M. Guyer - Northboro MA
Dan R. Huck - Shrewsbury MA
Michael F. Hunt - Ashland MA
David L. Keating - Holliston MA
Jeff S. Kimmell - Chapel Hill NC
Phil J. Roux - Holliston MA
Liz M. Truebenbach - Sudbury MA
Rob P. Valentine - Auburn MA
Pat J. Weiler - Northboro MA
Joseph Cox - Middleboro MA
Barry E. Gillott - Fairport NY
Andrea Heyda - Acton MA
Rob J. Pike - Northboro MA
Tom V. Radogna - Westboro MA
Art A. Sherman - Maynard MA
Michael Sporer - Wellesley MA
Doug J. Tucker - Northboro MA
Simon N. Yeung - Waltham MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 1300
G06F 112

US Classification:

395284

Abstract:

A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization.

US Patent:

61227560, Sep 19, 2000

Filed:

Feb 10, 1998

Appl. No.:

9/011721

Inventors:

William F. Baxter - Holliston MA
Robert G. Gelinas - Westboro MA
James M. Guyer - Northboro MA
Dan R. Huck - Shrewsbury MA
Michael F. Hunt - Ashland MA
David L. Keating - Holliston MA
Jeff S. Kimmell - Chapel Hill NC
Phil J. Roux - Holliston MA
Liz M. Truebenbach - Sudbury MA
Rob P. Valentine - Auburn MA
Pat J. Weiler - Northboro MA
Joseph Cox - Middleboro MA
Barry E. Gillott - Fairport NY
Andrea Heyda - Acton MA
Rob J. Pike - Northboro MA
Tom V. Radogna - Westboro MA
Art A. Sherman - Maynard MA
Micheal Sporer - Wellesley MA
Doug J. Tucker - Northboro MA
Simon N. Yeung - Waltham MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 1100

US Classification:

714 30

Abstract:

A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein. The system further includes a scan chain that electrically interconnects functionalities mounted on each motherboard and each of the at least one daughter board to the test bus controller; and an applications program for execution with said microcontroller. The applications program including instructions and criteria to automatically test the functionalities and electrical connections and interconnections, to automatically determine the presence of one or more faulted components and to automatically functionally remove the faulted component(s) from the computer system.