David Anthony Keating

US Patent:

44096550, Oct 11, 1983

Filed:

Apr 25, 1980

Appl. No.:

6/143981

Inventors:

Steven Wallach - Framingham MA
Kenneth D. Holberger - North Grafton MA
David L. Keating - Natick MA
Steven M. Staudaher - Northboro MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 900
G06F 932
G06F 934

US Classification:

364200

Abstract:

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.

US Patent:

45919720, May 27, 1986

Filed:

Nov 15, 1982

Appl. No.:

6/441969

Inventors:

James M. Guyer - Marlboro MA
David I. Epstein - Framingham MA
David L. Keating - Holliston MA

Assignee:

Data General Corp. - Westborough MA

International Classification:

G06F 916
G06F 1300

US Classification:

364200

Abstract:

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a multifunction nibble shifter, and a high speed look-aside memory control. Adaptive microcode control means 272 are disclosed in which microinstruction sequencing is a function 273 of the current microinstruction and current machine state.

US Patent:

45970416, Jun 24, 1986

Filed:

Nov 15, 1982

Appl. No.:

6/441839

Inventors:

James M. Guyer - Marlboro MA
David I. Epstein - Framingham MA
David L. Keating - Holliston MA
Walker Anderson - Arlington MA
James E. Veres - Framingham MA
Harold R. Kimmens - Hudson MA

Assignee:

Data General Corp. - Westborough MA

International Classification:

G06F 924

US Classification:

364200

Abstract:

A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.