David N Knapp

US Patent:

6470486, Oct 22, 2002

Filed:

May 17, 2000

Appl. No.:

09/574693

Inventors:

David Knapp - San Jose CA

Assignee:

Get2Chip - San Jose CA

International Classification:

G06F 1750

US Classification:

716 18, 716 10, 716 8, 716 7, 716 6, 716 3, 716 2

Abstract:

A delay-optimizing technology-mapping process for an electronic design automation system selects the best combination of library devices to use in a forward and a backward sweep of circuit trees representing a design. A technology selection process in an electronic design automation-system comprises the steps of partitioning an original circuit design into a set of corresponding logic trees. Then, ordering the set of corresponding logic trees into an ordered linear list such that each tree-T that drives another ordered tree precedes the other ordered tree, and such that each ordered tree that drives the tree-T precedes the tree-T. Next, sweeping forward in the ordered linear list while computing a set of Pareto-optimal load/arrival curves for each of a plurality of net nodes that match a technology-library element. And, sweeping backward in the ordered linear list while using the set of Pareto-optimal load/arrival curves for each of the net nodes and a capacitive load to select a best one of the technology-library elements with a shortest signal arrival time. Wherein, only those net nodes that correspond to gate inputs are considered, and any capacitive loads are predetermined.

US Patent:

6505339, Jan 7, 2003

Filed:

Jan 4, 2000

Appl. No.:

09/476884

Inventors:

Ronald A. Miller - Mountain View CA
Donald B. MacMillen - Redwood Shores CA
Tai A. Ly - San Jose CA
David W. Knapp - Palo Alto CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A method and an apparatus for coupling the results of behavioral synthesis with those of logic synthesis. It uses a timing verifier to precalculate the timing characteristics of a circuit for use by behavioral synthesis. Timing for control chaining is included in the precalculated timing characteristics. Once behavioral synthesis is complete, logic synthesis is informed of timing constraints introduced by behavioral synthesis.

US Patent:

6516453, Feb 4, 2003

Filed:

May 17, 2000

Appl. No.:

09/574572

Inventors:

David Knapp - San Jose CA

Assignee:

Get2Chip - San Jose CA

International Classification:

H06F 1750

US Classification:

716 6, 364489, 364490, 364491, 395558

Abstract:

A design-timing-determination process for an electronic design automation system approximates the timing of a whole design quickly and on-the-fly. Such allows a scheduling system to construct operation schedules that are ultimately realizable. A timing analysis is applied each time an individual operation is scheduled, and may be called many times to get a single operation scheduled. A graph representing combinational logic is partitioned into a collection of logic trees with nodes that represent gates and terminals, and arcs that represent connections. A compacted model of each logic tree is constructed by replacing them with equivalent trees having no interior nodes. The timing of the original circuit is analyzed along each path from the leaves to the roots. A propagation delay for each path is determined, and such is annotated onto each corresponding arc of the simplified tree. Any dependency of the propagation delay in the original circuit on the slew rate of their input signals is annotated onto the corresponding leaf of the simplified tree.

US Patent:

6782511, Aug 24, 2004

Filed:

May 25, 2000

Appl. No.:

09/579825

Inventors:

Elof Frank - Sunnyvale CA
Bernd Braune - Menlo Park CA
David Knapp - San Jose CA
Pradeep Fernandes - San Jose CA
Hans-Joachim Schmidt - Munich, DE

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 1, 716 18, 716 3, 716 9, 716 10

Abstract:

A business-to-business application service provider includes an Internet website and webserver with EDA-on-demand solutions for system-on-a-chip designers. Such website allows electronic designs in hardware description language to be uploaded into a front-end EDA design environment. A behavioral model simulation tool hosted privately on the webserver tests and validates the design. Such tool executes only in the secure environment of the business-to-business application service provider. The validated solution is then downloaded back over the Internet for a pay-per-use fee to the customer, and in a form ready to be placed and routed by a back-end EDA tool. Such validated design solutions are also downloadable to others in exchange for other designs, or available in technology libraries. The intellectual property created can be re-used, sold, shared, exchanged, and otherwise distributed efficiently and easily from a central for-profit clearinghouse.

US Patent:

7584441, Sep 1, 2009

Filed:

Sep 19, 2003

Appl. No.:

10/665880

Inventors:

Alexander Gidon - Karlsfeld, DE
David Knapp - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 6

Abstract:

A method for generating timing constraint systems, where the constrained object is a digital circuit. , is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

US Patent:

RE40925, Sep 29, 2009

Filed:

Jun 8, 2000

Appl. No.:

09/590584

Inventors:

Tai A. Ly - San Jose CA, US
David W. Knapp - San Jose CA, US
Ronald A. Miller - Cupertino CA, US
Donald B. Macmillen - Redwood City CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 1

Abstract:

A method and an apparatus for creating a representation of a circuit with a pipelined loop from an HDL source code description. It infers a circuit including a pipelined loop which has cycle level simulation behavior matching that of the source HDL. Loop carry dependencies and memory and signal I/O accesses within the loop are scheduled correctly.

US Patent:

8060844, Nov 15, 2011

Filed:

Nov 26, 2008

Appl. No.:

12/324742

Inventors:

Alexander Gidon - Karlsfeld, DE
David Knapp - Sunnyvale CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716101, 716104, 716108, 716113, 716132, 716134

Abstract:

A method for generating timing constraint systems, where the constrained object is a digital circuit, is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design. The invention comprises a method that comprises the following steps: (1) the flip-flops of the design are replaced with buffers having a negative delay whose magnitude is approximately the desired clock cycle time of the design; and (2) cycles in the design are broken using flip-flops having an infinite or quasi-infinite clock frequency. Following optimization by the synthesis tool, the temporary changes can be reverted, and retiming performed on the circuit.

US Patent:

20140023785, Jan 23, 2014

Filed:

Jul 23, 2012

Appl. No.:

13/555832

Inventors:

David Knapp - Santa Clara CA, US
David Thompson - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 16/18

US Classification:

427252

Abstract:

Provided are precursors and methods of using same to deposit film consisting essentially of nickel. Certain methods comprise providing a substrate surface; exposing the substrate surface to a vapor comprising a precursor having a structure represented by formula (I):wherein Ris t-butyl and each Ris each independently any C1-C3 alkyl group; and exposing the substrate to a reducing gas to provide a film consisting essentially of nickel on the substrate surface.