David T Kramer

US Patent:

6850516, Feb 1, 2005

Filed:

Mar 2, 2001

Appl. No.:

09/798472

Inventors:

Victor A. Bennett - Rockwall TX, US
Leslie Zsohar - Round Rock TX, US
Shannon E. Lawson - Pflugerville TX, US
Sean W. McGee - Austin TX, US
David P. Sonnier - Austin TX, US
David B. Kramer - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 1250

US Classification:

370357, 370392, 37039552, 370474

Abstract:

A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

US Patent:

7009979, Mar 7, 2006

Filed:

Mar 30, 2001

Appl. No.:

09/822655

Inventors:

David B. Kramer - Austin TX, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/28

US Classification:

37039552, 370466, 370474, 370401

Abstract:

A virtual segmentation system for use with a routing switch processor and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to receive at least a portion of a protocol data unit and assemble the protocol data unit. The virtual segmentation system further includes a virtual segmentation subsystem that is associated with the protocol data unit receiver subsystem and is configured to perform virtual segmentation on the protocol data unit.

US Patent:

7116680, Oct 3, 2006

Filed:

Mar 2, 2001

Appl. No.:

09/798112

Inventors:

David B Kramer - Austin TX, US
David P Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/56
H04J 3/22

US Classification:

370465, 3703954

Abstract:

A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet.

US Patent:

7149211, Dec 12, 2006

Filed:

Nov 19, 2004

Appl. No.:

10/993627

Inventors:

Victor A. Bennett - Rockwall TX, US
Leslie Zsohar - Round Rock TX, US
Shannon E. Lawson - Pflugerville TX, US
Sean W. McGee - Austin TX, US
David P. Sonnier - Austin TX, US
David B. Kramer - Austin TX, US

Assignee:

Agere Systems Inc. - Allowtown PA

International Classification:

H04L 12/50

US Classification:

370357, 370392, 37039552

Abstract:

A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

US Patent:

7159061, Jan 2, 2007

Filed:

Dec 23, 2003

Appl. No.:

10/744567

Inventors:

Asif Q. Khan - Austin TX, US
David B. Kramer - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H03M 7/20
G06F 12/00
G06F 13/14
G06F 13/00
G06F 11/00

US Classification:

710305, 370229, 370394, 370449, 370466, 370516, 37039542, 710 3, 710 33, 710100, 709232, 341102

Abstract:

Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

US Patent:

7215675, May 8, 2007

Filed:

Feb 28, 2002

Appl. No.:

10/085771

Inventors:

David B. Kramer - Austin TX, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

3703954

Abstract:

A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

US Patent:

7224681, May 29, 2007

Filed:

Feb 28, 2002

Appl. No.:

10/085223

Inventors:

David B. Kramer - Austin TX, US
David P. Sonnier - Austin TX, US
Leslie Zsohar - Round Rock TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04B 7/212
H04L 12/28
H04L 12/56

US Classification:

370347, 3703954

Abstract:

A processor includes scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements. The scheduling circuitry has at least one time slot table accessible thereto, and is configured for utilization of the time slot table in scheduling the data blocks for transmission. The time slot table includes a plurality of locations, with each of the locations corresponding to a transmission time slot and being configurable for storing identifiers of at least two of the transmission elements. In an illustrative embodiment, a given one of the locations in the time slot table stores in a first portion thereof an identifier of a first one of the transmission elements that has requested transmission of a block of data in the corresponding time slot, and stores in a second portion thereof an identifier of a second one of the transmission elements that has requested transmission of a block of data in the corresponding time slot. Furthermore, additional transmission elements generating colliding requests for the given location can be linked between the first and second transmission elements using a linking mechanism. The use of multi-entry time slot table locations to accommodate collisions between transmission element requests considerably facilitates the maintenance of desired traffic shaping requirements.

US Patent:

7245624, Jul 17, 2007

Filed:

Feb 28, 2002

Appl. No.:

10/085222

Inventors:

David B. Kramer - Austin TX, US
David P. Sonnier - Austin TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H04L 12/56

US Classification:

3703954, 370411

Abstract:

A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements. The interval computation element operates under software control in at least one of determining and adjusting the transmission interval, and may be operative to determine periodically if the transmission interval requires adjustment in order to maintain the desired service level for one or more of the transmission elements.