David P Lutz

US Patent:

7219214, May 15, 2007

Filed:

Jul 13, 2004

Appl. No.:

10/889318

Inventors:

Simon Andrew Ford - Cambridge, GB
Dominic Hugo Symes - Cambridge, GB
Andrew Christopher Rose - Cambridge, GB
David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/00
G06F 9/44

US Classification:

712225, 712 22, 712223, 711154

Abstract:

A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

US Patent:

7219215, May 15, 2007

Filed:

Jul 13, 2004

Appl. No.:

10/889367

Inventors:

Simon Andrew Ford - Cambridge, GB
Dominic Hugo Symes - Cambridge, GB
Andrew Christopher Rose - Cambridge, GB
David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/40

US Classification:

712225, 712223, 712 22

Abstract:

A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

US Patent:

7356553, Apr 8, 2008

Filed:

Mar 18, 2004

Appl. No.:

10/803164

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/465

US Classification:

708505

Abstract:

The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data element specifying a second exponent. The data processing apparatus comprises processing logic providing multiple processing paths which are selectable to perform the data processing operation, including a first processing path operable to perform the data processing operation if a predetermined alignment condition exists. Further, at least one detector logic unit is provided which is operable to receive both the first exponent and the second exponent and to detect the presence of the predetermined alignment condition. Each detector logic unit comprises half adder logic operable to perform a half adder operation to logically subtract one of the first and second exponents from the other of the first and second exponents to produce at least a sum data value of sum and carry data values representing the result of the half adder operation. Further, each detector logic unit comprises generation logic operable to receive the sum data value and to generate a select signal which is set if the sum data value has a predetermined value indicating the existence of the predetermined alignment condition.

US Patent:

7386580, Jun 10, 2008

Filed:

Mar 18, 2004

Appl. No.:

10/803162

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

Arm Limited - Cambridge

International Classification:

G06F 15/00

US Classification:

708201

Abstract:

A data processor computes an absolute difference between portions of first and second data elements. At least a part of the first and second data elements are compared to determine which data element is larger. A first comparison result value is produced if the first element is larger and a second comparison result value if the second element is larger. An absolute difference is computed between a portion of the first and second data elements. One of the portions is inverted and added to the other portion and to the comparison result to produce an intermediate result. An absolute difference is provided with improved speed either as the intermediate result or an inverted version of the intermediate result dependent on the comparison result.

US Patent:

7401107, Jul 15, 2008

Filed:

Dec 22, 2004

Appl. No.:

11/019097

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 5/00

US Classification:

708204

Abstract:

A data processing apparatus and method are provided for converting an m-bit fixed point number to a rounded floating point number having an n-bit significand, where n is less than m. The data processing apparatus comprises determination logic for determining the bit location of the most significant bit of the value expressed within the m-bit fixed point number, and low order bit analysis logic for determining from a selected number of least significant bits of the m-bit fixed point number a rounding signal indicating whether a rounding increment is required in order to generate the n-bit significand. Generation logic is then arranged in response to the rounding signal to generate a rounding bit sequence appropriate having regard to the bit location determined by the determination logic. Adder logic then adds the rounding bit sequence to the m-bit fixed point number to generate an intermediate result, whereafter normalisation logic shifts the intermediate result to generate the n-bit significand. At this point, due to the incorporation of the rounding information prior to the addition, the generated n-bit significand is correctly rounded.

US Patent:

7433911, Oct 7, 2008

Filed:

Dec 21, 2004

Appl. No.:

11/017217

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/483

US Classification:

708505

Abstract:

A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand. First adder logic is then operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic. Further, second adder logic is provided to perform a second sum operation in order to generate a second rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic also comprising a single level of adder logic. Selector logic is then used to derive the n-bit result from either the first rounded result or the second rounded result.

US Patent:

7437400, Oct 14, 2008

Filed:

Mar 14, 2005

Appl. No.:

11/078699

Inventors:

David Raymond Lutz - Austin TX, US
Christopher Neal Hinds - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/485

US Classification:

708505

Abstract:

A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floating point operands is the larger operand. First adder logic is used, if predetermined criteria exists, to perform an addition of the n-bit significands of the first and second floating point operands to produce the sum value, whilst second adder logic is used, if the predetermined criteria does not exist, to perform that addition. Result logic can then derive the n-bit result from either an output of the first adder logic or an output of the second adder logic. If the addition is a like-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require an effective 1-bit right shift to normalise the sum value, whereas if the addition is an unlike-signed addition, the predetermined criteria is determined to exist for a set of situations where the sum value produced by the first adder logic will require at least an effective 1-bit left shift to normalise the sum value.

US Patent:

7599974, Oct 6, 2009

Filed:

Mar 22, 2004

Appl. No.:

10/805502

Inventors:

Christopher Neal Hinds - Austin TX, US
David Raymond Lutz - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 7/00

US Classification:

708200

Abstract:

A data processing apparatus compares first and second floating point operands to produce a comparison result. For each floating point operand, a first component is derived from a predetermined number of MSBs of the fraction component which is less than the total number of bits constituting the fraction component. The sign and exponent components of the first and second floating point operands are compared to produce a plurality of signals. If possible, the comparison result is determined from the plurality of signals. For each floating point operand, a second component is derived from the bits of the fraction component of that floating point operand other than the predetermined number of MSBs. The second components of the first and second floating point operands to are compared produce a further signal. The comparison result is determined from the plurality of signals and the further signal.