David S Masters

US Patent:

8489791, Jul 16, 2013

Filed:

Dec 28, 2010

Appl. No.:

12/979551

Inventors:

Richard J. Byrne - Hillsborough NJ, US
David S. Masters - Schnecksville PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 13/26
G06F 13/40

US Classification:

710306, 710311

Abstract:

Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching.

US Patent:

8489792, Jul 16, 2013

Filed:

Dec 28, 2010

Appl. No.:

12/979665

Inventors:

Richard J. Byrne - Hillsborough NJ, US
David S. Masters - Schnecksville PA, US
Steven J. Pollock - Allentown PA, US
Michael R. Betker - Orefield PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 13/36

US Classification:

710306, 709230

Abstract:

Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated.

US Patent:

20130042038, Feb 14, 2013

Filed:

Mar 1, 2012

Appl. No.:

13/409432

Inventors:

Richard J. Byrne - Hillsborough NJ, US
David S. Masters - Schnecksville PA, US

International Classification:

G06F 13/36
G06F 13/362

US Classification:

710113, 710310

Abstract:

Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.