David W Mccarroll

US Patent:

7667498, Feb 23, 2010

Filed:

Oct 23, 2008

Appl. No.:

12/288754

Inventors:

David W. McCarroll - Florissant CO, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03K 19/096

US Classification:

326 95, 326 93, 326 98

Abstract:

A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal that is an inverse of the input signal. A first inverter receives the output signal from the first transistor stack. A second transistor stack receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and generates an output signal that is an inverse of an output signal from the first inverter. A pass control circuit includes first and second transistors. The first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack.

US Patent:

8076956, Dec 13, 2011

Filed:

Feb 22, 2010

Appl. No.:

12/709736

Inventors:

David W. McCarroll - Florissant CO, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03K 19/096

US Classification:

326 95, 326 93, 326 98

Abstract:

A circuit includes a first transistor stack that receives an input signal, a voltage reference, a reference potential, a clock signal and an inverted clock signal, and generates an output signal that is an inverse of the input signal. A first inverter receives the output signal from the first transistor stack. A second transistor stack receives the voltage reference, the reference potential, the clock signal and the inverted clock signal, and generates an output signal that is an inverse of an output signal from the first inverter. A pass control circuit includes first and second transistors. The first terminals of the first and second transistors are coupled together and receive the output signal of the second transistor stack, control terminals of the first and second transistors receive the clock signal and the inverted clock signal, respectively, and second terminals of the first and second transistors are coupled together and output the output signal of the second transistor stack.

US Patent:

20060145724, Jul 6, 2006

Filed:

Dec 31, 2004

Appl. No.:

11/026530

Inventors:

David McCarroll - Florissant CO, US

International Classification:

H03K 19/094

US Classification:

326083000

Abstract:

Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be maintained in the storage elements.

US Patent:

20060145725, Jul 6, 2006

Filed:

May 18, 2005

Appl. No.:

11/132618

Inventors:

David McCarroll - Florissant CO, US

International Classification:

H03K 19/094

US Classification:

326083000

Abstract:

Circuits and techniques to, during a lower power state, power down combinational logic and to maintain power to storage elements associated with the combinational logic. By powering down the combinational logic gates, leakage current may be reduced and state, or other, values to be used for subsequent operations may be maintained in the storage elements.