David R Mccubbrey

US Patent:

6647891, Nov 18, 2003

Filed:

Dec 13, 2001

Appl. No.:

10/013530

Inventors:

Quentin Holmes - Springfield OR
Paul Kortesoja - Ann Arbor MI
David McCubbrey - Ann Arbor MI
Joseph Samson - Brighton MI
Thomas Wessling - Howell MI
Lester Witter - Saline MI
Robert Rendleman - Anacortes WA
John Blanchfield - Mooresville NC
Gregory Lowe - Moneta VA

Assignee:

Norfolk Southern Corporation - Norfolk VA

International Classification:

E01B 902

US Classification:

104 2, 25055931, 356602

Abstract:

A method and an apparatus for identifying a feature of a railway and deploying equipment for servicing same by image processing range data pertaining to the railway feature. The method includes identifying a feature of a railway, wherein the identifying involves processing an image corresponding to ranges to the feature. The apparatus includes a vision system for determining a range to a feature of the railway and means for positioning equipment relative to, for servicing, the feature, based on the range.

US Patent:

7073158, Jul 4, 2006

Filed:

May 19, 2003

Appl. No.:

10/441581

Inventors:

David L. McCubbrey - Ann Arbor MI, US

Assignee:

Pixel Velocity, Inc. - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716 17, 716 18

Abstract:

An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.

US Patent:

7451410, Nov 11, 2008

Filed:

Nov 26, 2004

Appl. No.:

10/998020

Inventors:

David L. McCubbrey - Ann Arbor MI, US

Assignee:

Pixel Velocity Inc. - Ann Arbor IL

International Classification:

G06F 17/50

US Classification:

716 1, 716 12, 716 17, 716 19

Abstract:

The stackable motherboard of the first embodiment includes: a circuit board having a first side and a second side opposite the first side , a processor mounted on the circuit board , a first peripheral interconnect , and a second peripheral interconnect. The stackable motherboard also preferably includes: a first motherboard interconnect mounted on the first side of the circuit board and adapted to communicate data between the processor and a first auxiliary motherboard, and a second motherboard interconnect mounted on the second side of the circuit board and adapted to communicate data between the processor and a second auxiliary motherboard.

US Patent:

7587699, Sep 8, 2009

Filed:

May 10, 2006

Appl. No.:

11/432186

Inventors:

David L. McCubbrey - Ann Arbor MI, US

Assignee:

Pixel Velocity, Inc. - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716 17, 716 6, 716 9, 716 12

Abstract:

An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.

US Patent:

8230374, Jul 24, 2012

Filed:

Dec 14, 2007

Appl. No.:

11/957287

Inventors:

David L. McCubbrey - Ann Arbor MI, US

Assignee:

Pixel Velocity, Inc. - Ann Arbor MI

International Classification:

G06F 17/50

US Classification:

716116, 716101, 716105

Abstract:

A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.

US Patent:

8587661, Nov 19, 2013

Filed:

Feb 21, 2008

Appl. No.:

12/035395

Inventors:

David L. McCubbrey - Ann Arbor MI, US

Assignee:

Pixel Velocity, Inc. - Ann Arbor MI

International Classification:

H04N 7/18
G06K 9/62

US Classification:

348159, 382209

Abstract:

According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.

US Patent:

20080036864, Feb 14, 2008

Filed:

Aug 8, 2007

Appl. No.:

11/891516

Inventors:

David McCubbrey - Ann Arbor MI, US
Eric Sieczka - Ann Arbor MI, US

International Classification:

H04N 7/18

US Classification:

348159000

Abstract:

A method and system for capturing and transmitting image data streams. In one embodiment, the method includes capturing image data with a image sensor; creating a window within the image data and creating a detailed image data stream based on the windowed image data; reducing the image data and creating a contextual image data stream based on the reduced image data; and transmitting the detailed image data stream and the contextual image data stream.

US Patent:

20080151049, Jun 26, 2008

Filed:

Dec 14, 2007

Appl. No.:

11/957304

Inventors:

David L. McCubbrey - Ann Arbor MI, US
Eric Sieczka - Ann Arbor MI, US

International Classification:

H04N 7/18
H04N 7/00

US Classification:

348143, 348 36, 348159, 382154, 348E07085, 348E07086, 348E07091

Abstract:

In one embodiment, the gaming surveillance system includes a camera subsystem, wherein the camera subsystem contains a means for extracting features in real-time, an image server, wherein the image server is connected to the camera subsystem, and communicates with the camera subsystem, and a client connected to the image server, wherein the client receives a data stream from the image server, wherein the data stream includes metadata. In another embodiment, the method of extracting metadata from multiple synchronized cameras includes the steps of capturing a first set of images and a second set of images from multiple synchronized cameras, processing the first set of images and the second set of images, and outputting metadata from the processed image sets.