David J Mcintyre

US Patent:

7036068, Apr 25, 2006

Filed:

Jul 25, 2001

Appl. No.:

09/915194

Inventors:

James Andrew Davis - Richmond VA, US
Jonathan Jedwab - Bristol, GB
David H. McIntyre - Boise ID, US
Kenneth Graham Paterson - Teddington, GB
Frederick A Perner - Palo Alto CA, US
Gadiel Seroussi - Cupertino CA, US
Kenneth K Smith - Boise ID, US
Stewart R. Wyatt - Boise ID, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 29/00

US Classification:

714763, 714752, 714746

Abstract:

A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols in a block of ECC encoded data which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells. Where the position of suspected failed symbols is known from this erasure information, the ability of a decoder to perform ECC decoding is substantially enhanced.

US Patent:

8503210, Aug 6, 2013

Filed:

Dec 22, 2010

Appl. No.:

12/975601

Inventors:

Mandeep Singh - Austin TX, US
David Hugh McIntyre - Sunnyvale CA, US
Hung Phuong Ngo - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 15/04
G11C 15/00

US Classification:

365 4917, 365 491, 365203, 711108

Abstract:

A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

US Patent:

20030172339, Sep 11, 2003

Filed:

Mar 8, 2002

Appl. No.:

10/093834

Inventors:

James Davis - Richmond VA, US
Jonathan Jedwab - London, GB
Gadiel Seroussi - Cupertino CA, US
David Banks - Bristol, GB
David McIntyre - Boise ID, US
Stewart Wyatt - Boise ID, US

International Classification:

G11C029/00

US Classification:

714/763000

Abstract:

A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. A linear error correction block code such as a Reed-Solomon code forms codewords having a plurality of symbols. In almost all cases, a corrected codeword is formed by error correction decoding a read codeword in a standard first decoder arranged to reliably identify and correct up to a predetermined number of failed symbols, or else determine an unrecoverable error. Error correction decoding of the read codeword is then attempted in a stronger second decoder, ideally being a maximum likelihood decoder arranged to form one or more closest corrected codewords. Optionally, erasure information predicting failed symbols is used to enhance the error correction decoding

US Patent:

20200090736, Mar 19, 2020

Filed:

Sep 14, 2018

Appl. No.:

16/132003

Inventors:

- Santa Clara CA, US
Ravi Jotwani - Austin TX, US
David Hugh McIntyre - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G11C 11/419
G11C 11/418
G11C 5/14
G11C 7/12
G11C 7/10

Abstract:

A write driver includes a first write data driver, a second write driver, and a control circuit. The first (second) write data driver provides a true (complement) write data signal to an output thereof at a high voltage when a true (complement) data signal is in a first logic state, at a ground voltage when the true (complement) data signal is in a second logic state and a negative bit line enable signal is inactive, and at a voltage below the ground voltage when the true (complement) data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold, and in an inactive state when the power supply voltage is above a second threshold higher than the first threshold.

US Patent:

20180226111, Aug 9, 2018

Filed:

Feb 3, 2017

Appl. No.:

15/424418

Inventors:

- Sunnyvale CA, US
Ravi T. Jotwani - Austin TX, US
Samiul Haque Khan - Austin TX, US
David Hugh McIntyre - Sunnyvale CA, US
Stephen Victor Kosonocky - Ft. Collins CO, US
John J. Wuu - Fort Collins CO, US
Russell Schreiber - Austin TX, US

International Classification:

G11C 8/08
G06F 3/06

Abstract:

A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.