David M Morrill

US Patent:

6344958, Feb 5, 2002

Filed:

Feb 10, 2000

Appl. No.:

09/501869

Inventors:

David P. Morrill - Scarborough ME

Assignee:

Fairchild Semiconductor Corp. - South Portland ME

International Classification:

H02H 320

US Classification:

361 915

Abstract:

An overvoltage protection circuit arranged to sense removal of the overvoltage condition. The protection circuit blocks current passing through a pull up transistor of an output circuit to a high-potential supply rail during an overvoltage condition applied at a common bus. The protection circuit includes one protection branch controlled by the potential at the bus and powered by the high-potential supply rail of the output circuit to be protected. The protection circuit also includes a second protection branch controlled by the high-potential supply rail and powered by the potential on the bus. When an overvoltage condition occurs, the second branch is activated and regulates an output from the first protection branch. That output signal controls the control node of the pull up transistor of the output circuit to be protected. The two protection branches are configured such that removal of the overvoltage condition causes a rapid changing of the state of the output of the first protection branch so that the operating condition of the pull up transistor remains the same as it was prior to the overvoltage condition.

US Patent:

7248122, Jul 24, 2007

Filed:

Sep 14, 2005

Appl. No.:

11/226047

Inventors:

David P. Morrill - Scarborough ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03L 7/085

US Classification:

331 1A, 331 17

Abstract:

A clock circuit for outputting serial data without using a PLL is described. The clock is a VCO designed to start at a frequency that is slightly higher than necessary to preserve the data. The frequency of the clock is measured and if the frequency is too high or too low the DC control voltage for the VCO is changed to bring the VCO frequency back to the start frequency. Clock counters, holding registers, comparators, and a D/A form a feed back path around a VCO. In addition, a word boundary generator is used to define individual data words. The word boundary is formed by the absence of a bit clock transition while there is a data bit transition. A high/low threshold may be used where the VCO frequency, as measured, must transcend a threshold before the DC control voltage to the VCO is changed.

US Patent:

7756659, Jul 13, 2010

Filed:

Jan 11, 2008

Appl. No.:

11/972997

Inventors:

David P. Morrill - Scarborough ME, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

G01D 18/00

US Classification:

702 89, 702117, 702118, 702125, 702176, 331 2, 331 46

Abstract:

In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.

US Patent:

60609389, May 9, 2000

Filed:

Aug 19, 1998

Appl. No.:

9/136246

Inventors:

David P. Morrill - Portland ME

Assignee:

Fairchild Semiconductor Corp. - South Portland ME

International Classification:

H03K 1716
H03K 17687

US Classification:

327391

Abstract:

An output buffer for reducing the signal noise associated with the switching between logic high and logic low electrical. Signals includes a first clamping circuit linked to the pull-up output transistor of the buffer, and a second clamping circuit linked to the pull-down output transistor of the buffer. The buffer may include both clamping circuits or either the first or second clamping circuit alone, dependent upon signal shaping interests. Each of the clamping circuits includes a selectable delay stage coupled to the buffer's input, a current regulator controlled by the delay stage, and a clamping device that is coupled to the control node of the output transistor. When the current regulator is conducting, the control node of the output transistor is clamped at a potential near its threshold turn-on. As a result, when the clamping circuit is turned off, the output transistor experiences a soft turn-on, thereby reducing signal bounce and the associated noise.

US Patent:

61508454, Nov 21, 2000

Filed:

Jun 1, 1999

Appl. No.:

9/323868

Inventors:

David P. Morrill - Portland ME

Assignee:

Fairchild Semiconductor Corp. - South Portland ME

International Classification:

H03K 190185

US Classification:

326 81

Abstract:

A CMOS-based bus-hold circuit having overvoltage tolerance. The bus-hold circuit of the present invention includes, in addition to conventional input and latching inverters, a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter. The sense circuit includes a comparator designed to compare the potential of a standard high-potential power supply rail to the potential associated with a signal applied to the bus-hold circuit's input node. The higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high-potential power rail. The pseudo high-potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions, particularly when the circuit is in its high-impedance state. The bus-hold circuit may be similarly designed to establish an undervoltage tolerance as well.

US Patent:

62491482, Jun 19, 2001

Filed:

Feb 10, 2000

Appl. No.:

9/501249

Inventors:

David P. Morrill - Scarborough ME

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03K 19175

US Classification:

326 89

Abstract:

A variable base drive output circuit that is operational for low-potential power supplies. The output circuit includes a current regulating branch and a base drive branch. A control transistor is logically coupled to an enable signal and an input signal to be propagated. Activation of that control transistor establishes a current path to the base of a bipolar pulldown transistor that is coupled to output. The current regulating branch includes a resistance device in series with current limiting transistors. The resistance device is coupled to the control node of a base current transistor such that when the load on the output node drops, the current to the base of the pulldown transistor also drops. The result is a savings in Icc current for logic LOW signals at the output node. The variable base drive output circuit is operable for low supply potentials.

US Patent:

62153420, Apr 10, 2001

Filed:

Jul 14, 1999

Appl. No.:

9/353514

Inventors:

David P. Morrill - Scarborough ME

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03K 1722

US Classification:

327143

Abstract:

A power-on reset circuit for a dual-supply system. The reset circuit includes a voltage divider powered by the first power supply and a sub-circuit supplied by the second power supply. The output of the voltage divider is connected to a control node of the first reset sub-circuit that is otherwise powered by the second power supply. A second reset sub-circuit is strictly regulated and powered by the second power supply. The first reset sub-circuit provides for translation of a signal having a potential limited by the potential of the first supply into a signal having a potential associated with that of the second supply. Only when a control signal from the voltage divider reaches a certain potential, and the second power supply reaches a certain potential, is the first reset sub-circuit activated in a manner that results in a circuit output signaling both supplies are at a suitable potential. This is useful for hot insertion applications in dual-supply systems.

US Patent:

61604291, Dec 12, 2000

Filed:

Nov 12, 1998

Appl. No.:

9/190308

Inventors:

David P. Morrill - Scarborough ME

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H03K 1722

US Classification:

327143

Abstract:

A fabrication- and temperature-independent power-on reset circuit for providing improved control over live insertion of integrated circuitry. The reset circuit includes a comparator having an output terminal and two input terminals, one positive and one negative. One of the two terminals is coupled to a first threshold turn-on branch and the other terminal is coupled to a second threshold turn-on branch. Both threshold branches are referenced to ground but they supply different initial potentials to the terminals of the comparator. As a result, one terminal acting as the reference terminal holds the circuit output of the present invention at a potential designed to halt circuit power-on regardless of independent enable control pin signals. The other of the two terminals does not trigger switching of the comparator output until after a common supply power rail reaches a desired potential at initial turn-on. Referencing of the two threshold branches of the circuit to ground ensures that fabrication and temperature vagaries are effectively cancelled out.