David J Patrick

US Patent:

7463983, Dec 9, 2008

Filed:

May 25, 2007

Appl. No.:

11/807015

Inventors:

David G. Patrick - San Jose CA, US

Assignee:

Thermo Finnigan LLC - San Jose CA

International Classification:

G01N 31/00

US Classification:

702 28

Abstract:

A TOF mass spectrometer has a clock phase to time bin cycling device that distributes data among storage cells in a random or systematic pattern that cancels out errors due to binary clock path and/or binary signal line irregularities. Data for peaks acquired from plural shots during TOF analysis are distributed among plural binary clock paths and the storage cells such that errors from irregularities in the binary clock paths and/or binary signal lines are not predominant in any peak of a spectrum generated from the analysis.

US Patent:

47362936, Apr 5, 1988

Filed:

Apr 11, 1984

Appl. No.:

6/599644

Inventors:

David M. Patrick - Aurora IL

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G06F 1300

US Classification:

364200

Abstract:

In a processing system (10) comprising a main memory (102) for storing blocks (150) of four contiguous words (160) of information, a cache memory (101) for storing selected ones of the blocks, and a two-word wide bus (110) for transferring words from the main memory to the cache, the cache memory is implemented in two memory parts (301, 302) as a two-way interleaved two-way set-associative memory. One memory part implements odd words of one cache set (0), and even words of the other cache set (1), while the other memory part implements even words of the one cache set and odd words of the other cache set. Storage locations (303) of the memory parts are grouped into at least four levels (204) with each level having a location from each of the memory parts and each of the cache sets. The cache receives a block over the bus in two pairs of contiguous words. The cache memory is updated with both words of a word pair simultaneously.

US Patent:

20230011863, Jan 12, 2023

Filed:

Jul 12, 2021

Appl. No.:

17/373678

Inventors:

- Santa Clara CA, US
SAURABH HUKERIKAR - Santa Clara CA, US
PAUL RACUNAS - Landaff NH, US
NIRMAL RAJ SAXENA - LOS ALTOS HILLS CA, US
DAVID CHARLES PATRICK - MADISON AL, US
YIYANG FENG - San Jose CA, US
ABHIJEET GHADGE - San Jose CA, US
STEVEN JAMES HEINRICH - Madison AL, US
ADAM HENDRICKSON - San Jose CA, US
GENTARO HIROTA - Sunnyvale CA, US
PRAVEEN JOGINIPALLY - San Jose CA, US
VAISHALI KULKARNI - Sunnyvale CA, US
PETER C. MILLS - San Jose CA, US
SANDEEP NAVADA - San Jose CA, US
MANAN PATEL - San Jose CA, US
LIANG YIN - San Jose CA, US

International Classification:

G06F 11/10
G06F 11/07
G06F 11/14
G06F 12/1027
G06F 12/1018

Abstract:

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.