David S Poole

US Patent:

20060288134, Dec 21, 2006

Filed:

Sep 12, 2005

Appl. No.:

11/224738

Inventors:

David Baker - Chapel Hill NC, US
Christopher Basoglu - Bothell WA, US
Benjamin Cutler - Seattle WA, US
Gregorio Gervasio - Sunnyvale CA, US
Woobin Lee - Lynnwood WA, US
Yatin Mundkur - Sunnyvale CA, US
Toru Nojiri - Tokyo, JP
John O'Donnell - Seattle WA, US
David Poole - Mountain View CA, US
Ashok Raman - San Jose CA, US
Eric Rehm - Bainbridge Island WA, US
Radhika Thekkath - Palo Alto CA, US
John Poole - Salem OR, US

International Classification:

G06F 5/00

US Classification:

710052000

Abstract:

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.