David James Ray

US Patent:

6446167, Sep 3, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435861

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

711122, 711 3, 711118, 711119, 711133, 711137, 711144

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.

US Patent:

6460115, Oct 1, 2002

Filed:

Nov 8, 1999

Appl. No.:

09/435865

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

711122, 711137, 711213, 712207

Abstract:

A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

US Patent:

6535962, Mar 18, 2003

Filed:

Nov 8, 1999

Appl. No.:

09/435860

Inventors:

Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711137, 711122, 711204, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

US Patent:

6574712, Jun 3, 2003

Filed:

Apr 14, 2000

Appl. No.:

09/550180

Inventors:

James Allan Kahle - Austin TX
Michael John Mayfield - Austin TX
Francis Patrick OConnell - Austin TX
David Scott Ray - Georgetown TX
Edward John Silha - Austin TX
Joel M. Tendler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711137, 711122, 711213, 712207

Abstract:

A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

US Patent:

6915415, Jul 5, 2005

Filed:

Jan 7, 2002

Appl. No.:

10/042102

Inventors:

Michael John Mayfield - Austin TX, US
Francis Patrick O'Connell - Austin TX, US
David Scott Ray - Georgetown TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/30

US Classification:

712225, 712205, 711137

Abstract:

A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.

US Patent:

7953960, May 31, 2011

Filed:

Oct 18, 2005

Appl. No.:

11/252410

Inventors:

Kurt Alan Feiste - Austin TX, US
David Scott Ray - Georgetown TX, US
David Shippy - Austin TX, US
Albert James Van Norstrand, Jr. - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712216

Abstract:

A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.

US Patent:

8082423, Dec 20, 2011

Filed:

Aug 11, 2005

Appl. No.:

11/201683

Inventors:

Christopher Michael Abernathy - Austin TX, US
Kurt Alan Feiste - Austin TX, US
David Scott Ray - Georgetown TX, US
David Shippy - Austin TX, US
Albert James Van Norstrand, Jr. - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712218, 712244

Abstract:

A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.

US Patent:

20060224864, Oct 5, 2006

Filed:

Mar 31, 2005

Appl. No.:

11/097741

Inventors:

Jonathan DeMent - Austin TX, US
Kurt Feiste - Austin TX, US
David Ray - Georgetown TX, US
David Shippy - Austin TX, US
Albert Van Norstrand - Round Rock TX, US

International Classification:

G06F 9/30

US Classification:

712219000

Abstract:

A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could complete. The execution unit then takes over stalling until the non-pipelined instruction is actually completed. This allows the execution unit more time to accurately determine when the non-pipelined instruction will complete. Slightly before the execution unit has completed the instruction, it releases the stall to the issue logic. The timing of the execution unit releasing the stall signal is set so that a dependent instruction can bypass the result as soon as possible. In other words, the dependent instruction does not have to wait for the result to be written to the processor register file in order to obtain access to the result.