David Peter Rivera

US Patent:

56340451, May 27, 1997

Filed:

Nov 13, 1995

Appl. No.:

8/555456

Inventors:

Vernon B. Goler - Austin TX
Gary L. Miller - Round Rock TX
David Rivera - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1340
G06F 104

US Classification:

395559

Abstract:

Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e. g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e. g. 58) coupled to the same pin/status bus (e. g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.

US Patent:

45846987, Apr 22, 1986

Filed:

Nov 2, 1983

Appl. No.:

6/548177

Inventors:

James M. Sibigtroth - Austin TX
David Rivera - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 2138
H03K 2366

US Classification:

377110

Abstract:

A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable prescaler couples the clock generator output to the counter chain input for providing a predetermined divisor input to the counter chain. A postscaler operates in consonance with the programmable prescaler coupled to the counter chain output for providing a timer output compensated for the predetermined divisor input. In operation, the timer output has a frequency bearing a constant relationship to the clock generator output frequency independent of the predetermined divisor input of the programmable prescaler.

US Patent:

58128336, Sep 22, 1998

Filed:

Nov 13, 1995

Appl. No.:

8/555454

Inventors:

Vernon Bernard Goler - Austin TX
Gary Lynn Miller - Round Rock TX
David Rivera - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1340
G06F 104

US Classification:

395557

Abstract:

I/O control modules (25-29) include a timer bus (71, 72) which may be segmented anywhere along its length. As a result, the channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebases by their respective timer bus (71, 72). The channels within one timer bus block (e. g. 86) can be used to perform different function(s) with the potential for no loss of resolution because each channel in a timer bus block (e. g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). In one embodiment, one end of each timer bus (71, 72) is delineated by a master timer bus control channel (61, 63), and the other end of the timer bus is delineated by a slave timer bus control channel (62, 64).