David M Siegel

US Patent:

20020087828, Jul 4, 2002

Filed:

Dec 28, 2000

Appl. No.:

09/753052

Inventors:

Ravi Arimilli - Austin TX, US
David Siegel - Austin TX, US

Assignee:

International Business Machines Corporation

International Classification:

G06F015/00

US Classification:

712/032000

Abstract:

Disclosed is a fully-interconnected, heterogenous, multiprocessor data processing system. The data processing system topology has a plurality of processors each having unique characteristics including, for example, different processing speeds (frequency) and different cache topologies (sizes, levels, etc.). Second and third generation heterogenous processors are connected to a specialized set of pins, connected to the system bus. The processors are interconnected and communicate via an enhanced communication protocol and specialized SMP bus topology that supports the heterogeneous topology and enables newer processors to support full downward compatibility to the previous generation processors. Various processor functions are modified to support operations on either of the processors depending on which processor is assigned which operations. The enhanced communication protocol, operating system, and other processor logic enable the heterogenous multiprocessor data processing system to operate as a symmetric multiprocessor system.

US Patent:

20110154351, Jun 23, 2011

Filed:

Dec 21, 2009

Appl. No.:

12/642908

Inventors:

Daniel J. Henderson - Georgetown TX, US
Prabhakar N. Kudva - New York NY, US
Naresh Nayar - Rochester MN, US
Pia Naoko Sanda - Slingerlands NY, US
David W. Siegel - Austin TX, US
James L. Van Oosten - , US
James Xenidis - , US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/46

US Classification:

718104

Abstract:

An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality of resources for completion of the task in accordance with a level of quality of service in a service level agreement.

US Patent:

54918111, Feb 13, 1996

Filed:

Apr 20, 1992

Appl. No.:

7/871322

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395471

Abstract:

Apparatus and method for improving the rate of transfer of data in the context of a system memory operated in conjunction with a cache. In one form, mask bits in a mask bit register are associated to bytes of cache. The mask bits are changed in state when the corresponding byte in the cache is written. The mask bits are used in a reordered operating sequence to selectively write data from system memory into the cache after a write into cache. Data transfer performance is improved significantly in that the selective writing of data from system memory to cache can be completely eliminated when the mask bits indicate that a whole unit of the cache, typically a cache line, has been written during the data transfer into the cache.

US Patent:

52874826, Feb 15, 1994

Filed:

Jul 9, 1992

Appl. No.:

7/912043

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395425

Abstract:

A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Virtual memory addresses used by the input/output devices are translated into real addresses in the system memory. Virtual memory can be partitioned, with some virtual addresses being mapped to a second memory attached to the input/output bus.

US Patent:

52874575, Feb 15, 1994

Filed:

Apr 15, 1992

Appl. No.:

7/870159

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314
G06F 1516

US Classification:

395200

Abstract:

A DMA controller coupled to two separate buses controls the transfer of data between them. To effect a block data transfer, data is simultaneously read on one bus and written on the other. This allows data to be transferred between buses at the maximum transfer rate supported by the slower bus.

US Patent:

52376761, Aug 17, 1993

Filed:

Jan 13, 1989

Appl. No.:

7/297773

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
George A. Lerom - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1314

US Classification:

395550

Abstract:

A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

US Patent:

52747840, Dec 28, 1993

Filed:

Nov 13, 1991

Appl. No.:

7/791468

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395325

Abstract:

A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

US Patent:

51094908, Apr 28, 1992

Filed:

Jan 13, 1989

Appl. No.:

7/297772

Inventors:

Ravi K. Arimilli - Round Rock TX
Sudhir Dhawan - Austin TX
James O. Nicholson - Austin TX
David W. Siegel - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 100

US Classification:

395325

Abstract:

A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.