David John Squires

US Patent:

6803786, Oct 12, 2004

Filed:

Mar 11, 2003

Appl. No.:

10/386955

Inventors:

Goran Bilski - San Jose CA
Ralph D. Wittig - Menlo Park CA
Jennifer Wong - Fremont CA
David B. Squires - Palo Alto CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39

Abstract:

Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

US Patent:

58154043, Sep 29, 1998

Filed:

Oct 16, 1995

Appl. No.:

8/543531

Inventors:

F. Erich Goetting - Cupertino CA
David P. Schultz - San Jose CA
David B. Squires - Palo Alto CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 3107
G06F 1718
G11C 2900

US Classification:

364489

Abstract:

A method and apparatus for creating and utilizing a database of defective antifuses on a programmable logic device and comparing the list to a catalog of required connections in a design, wherein the process of comparing the two lists will determine whether the device, although flawed, is nonetheless compatible with the design to be implemented, thereby increasing device yield.

US Patent:

42901006, Sep 15, 1981

Filed:

Mar 24, 1980

Appl. No.:

6/132819

Inventors:

David R. Squires - Cupertino CA

Assignee:

Intersil, Inc. - Cupertino CA

International Classification:

H02M 3155

US Classification:

363 60

Abstract:

A voltage tripler for multiplying a DC voltage from a battery to provide a driving voltage for an LCD display in a digital clock. The circuit includes a charging capacitor and two storage capacitors and a plurality of switches for interconnecting the capacitors with the battery. The switches are controlled by means of driving circuitry which provides break-before-make type switching. The operation of the circuit is divided into four phases. During an initial phase the charging capacitor is charged to the voltage of the battery. During the second phase the charging capacitor is connected in parallel with one of the storage capacitors in order to transfer a portion of the charge to the storage capacitor. During the third phase the charging capacitor is again connected to the battery to recharge the charging capacitor. During the fourth phase, the charging capacitor is connected in parallel with the other storage capacitor so as to transfer charge to the storage capacitor.

US Patent:

44332823, Feb 21, 1984

Filed:

Dec 8, 1981

Appl. No.:

6/328519

Inventors:

David R. Squires - Los Altos CA

Assignee:

Intersil - Cupertino CA

International Classification:

G05F 156

US Classification:

323281

Abstract:

A voltage divider circuit is provided which can be fabricated as a portion of a monolithic integrated circuit without requiring any external capacitors. The voltage divider circuit has a pair of capacitors which are alternately switched between series connection and parallel connection to divide an input supply voltage. The voltage divider circuit can thereby provide a second supply voltage of one half the input supply voltage.