David S Wang

US Patent:

6374404, Apr 16, 2002

Filed:

Dec 16, 1998

Appl. No.:

09/216668

Inventors:

Mario Udo Brotz - Mountain View CA
David S. Wang - Fremont CA

Assignee:

Sony Corporation of Japan - Tokyo
Sony Electronics, Inc. - Park Ridge NJ

International Classification:

H04N 5445

US Classification:

725 46, 725 37, 725 40, 725136, 725112

Abstract:

A client-side intelligent device having background caching of web pages within a digital television (DTV) system and method of same. The present invention includes a digital television system having an intelligent device for interfacing with a user/viewer and controlling the display of information on a display screen. The intelligent device, in one embodiment, is a set-top-box, but could be any intelligent electronic device or computer system. The set-top-box is configured to receive a DTV signal (e. g. , land based cable or digital satellite system) that includes audio/visual information as well as data signals in a datacast format. The datacast format includes web pages, e. g. , in the HTML (hypertext markup language) format of the world wide web. The DTV broadcasters support multiple channels of information on which content providers can supply a domain of web pages on a periodic basis. The present invention is able to display viewer-selected web pages on the DTV system.

US Patent:

6429734, Aug 6, 2002

Filed:

Dec 19, 2001

Appl. No.:

10/024789

Inventors:

David Y. Wang - San Jose CA
Jyn-Bang Shyu - Cupertino CA

Assignee:

Neoaxiom Corporation - San Jose CA

International Classification:

H03F 345

US Classification:

327558, 327552, 327156, 330258

Abstract:

A loop filter circuit in a phase lock loop, which also includes a phase detector, a charge pump, and a voltage controlled oscillator (VCO). The loop filter circuit is comprised of two active filters and a common mode feedback control differential comparator (CMFCDC). The active filters process differential signals from the charge pump and output a pair of differential signals to the VCO. The CMFCDC provides a common mode feedback path to both active filters. The loop filter circuit eliminates common mode noise introduced by power supply and ground, and reduces phase jitter in the overall PLL circuits. Each of the active filters is comprised of two independent sets of passive elements that dictate the values of natural modes (poles) and transmission zeros (zeros) of the filtering modules. This allows PLL designers wider latitude in adjusting the unity gain bandwidth of the active loop filter, which contributes to a more stable and better performing PLL circuit.

US Patent:

6442593, Aug 27, 2002

Filed:

Feb 1, 1999

Appl. No.:

09/241201

Inventors:

David Shan-Ming Wang - Fremont CA
P. Robert Hsu - San Jose CA

Assignee:

Sony Corporation - Tokyo
Sony Electronics Inc. - Park Ridge NJ

International Classification:

G06F 1516

US Classification:

709206, 709207

Abstract:

A system allows users to send electronic mail messages having prioritized delivery. A server receives an electronic mail message that contains a specified priority or a specified time frame for delivery. The server determines a time frame for delivery and selects procedures to ensure delivery of the electronic mail message within the determined time frame. The server then provides the electronic mail message to the receiving account within the determined time frame.

US Patent:

6531905, Mar 11, 2003

Filed:

Dec 19, 2001

Appl. No.:

10/024816

Inventors:

David Y. Wang - San Jose CA

Assignee:

Neoaxiom Corporation - San Jose CA

International Classification:

H03K 3037

US Classification:

327218

Abstract:

A flip-flop circuit with metastability reduction having two internal flip-flops connected in a parallel configuration relative to an input line with a input data delay connected to the data input of one of the flip-flops. The outputs are combined and since at least one of the flip-flop outputs should be stable, if the output of one of the flip-flop goes into a metastable state, the output of the other flip-flop will stabilize it, thus producing a stable output.

US Patent:

D475054, May 27, 2003

Filed:

May 31, 2001

Appl. No.:

29/142733

Inventors:

Bradley Blackwood - San Jose CA
Nicholas Denhez - San Francisco CA
Daniel Philip Groebe - Lake Zurich IL
Amy A. Han - Palo Alto CA
Troy Hulick - Saratoga CA
Andrea Johnson - Los Altos CA
Lawrence Lam - San Jose CA
Philip S. McClendon - Cupertino CA
Steven Shiozaki - Belmont CA
David Wang - Sunnyvale CA
Sylvia Weiser - San Jose CA

Assignee:

Palm, Inc. - Milpitas CA

International Classification:

1402

US Classification:

D14434

US Patent:

6587282, Jul 1, 2003

Filed:

Aug 16, 2002

Appl. No.:

10/222296

Inventors:

David Y. Wang - Fremont CA
David M. Aikens - Chester CT

Assignee:

Therma-Wave, Inc. - Fremont CA

International Classification:

G02B 900

US Classification:

359797, 359661, 359785

Abstract:

The subject invention relates to broadband optical metrology tools for performing measurements of patterned thin films on semiconductor integrated circuits. Particularly a family of optical designs for broadband, multi-wavelength, DUV-IR (185900 nm) all-refractive optical systems. The designs have net focusing power and this is achieved by combining at least one positively powered optical element with one negatively powered optical element. The designs have small spot-size over the wavelength range spanning 185-900 nm with substantially reduced spherical aberration, axial color, sphero-chromatism and zonal spherical aberration. The refractive optical systems are broadly applicable to a large class of broadband optical wafer metrology tools including spectrophotometers, spectroscopic reflectometers, spectroscopic ellipsometers and spectroscopic scatterometers.

US Patent:

6597212, Jul 22, 2003

Filed:

Mar 12, 2002

Appl. No.:

10/097492

Inventors:

David Y. Wang - San Jose CA
Yu-Chi Cheng - Fremont CA

Assignee:

Neoaxiom Corporation - San Jose CA

International Classification:

H03B 1900

US Classification:

327117, 377 47

Abstract:

A phase interpolator circuit that produces 2 phase resolution elements using a control signal that has less than m bits. The circuit combines the function of a divide-by-N circuit with a phase interpolation circuit enabled by the use of a higher-speed clock as an input. By performing phase interpolation at a high speed and then slowing down the speed for the subsequent circuits, the phase resolution increases and fewer control bits are required.

US Patent:

6718092, Apr 6, 2004

Filed:

May 9, 2002

Appl. No.:

10/143362

Inventors:

David W. Wang - Saratoga CA
John C. Tsai - Saratoga CA

Assignee:

Fibera, Inc. - Santa Clara CA

International Classification:

G02B 634

US Classification:

385 37

Abstract:

A frequency processing system for detecting, tuning, or stabilizing light frequency or wavelength in a light beam produced by a light source. A grating block receives the light beam and may produce diffracted beams and a passed beam. The diffracted beams are received by respective detectors which produce measurement signals that are communicated to a processor. The processor then produces control signals that are communicated to the light source where they are usable for detecting, tuning, or stabilizing the light frequency or wavelength. The grating blocks particularly employ planar or cubical gratings, or gradient versions of these, to produce the diffracted beams.