David A Webber

US Patent:

7146520, Dec 5, 2006

Filed:

May 12, 2003

Appl. No.:

10/436210

Inventors:

Michael Billeci - Poughkeepsie NY, US
Timothy G. McNamara - Fishkill NY, US
Ching-Lung L. Tong - Highland Mills NY, US
David Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/04
G06F 1/14

US Classification:

713502, 713500, 713400, 713600

Abstract:

A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.

US Patent:

7376890, May 20, 2008

Filed:

May 27, 2004

Appl. No.:

10/855734

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Lawrence Joseph Powell - Round Rock TX, US
Martin Stanley Schmookler - Austin TX, US
Michael Thomas Vaden - Austin TX, US
David Allan Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/10

US Classification:

714808, 712 26

Abstract:

A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antimask of the mask is created, and the modulo of the antimask is calculated. A modulo function of the first result of the selected function is calculated to obtain a third result. A modulo of the operand is then calculated to obtain a fourth result, and a second function is then performed on the second result and the third result to obtain a fifth result. In response to comparing the fifth result to the fourth result, a signal is propagated to indicate a fault in the circuit.

US Patent:

7509365, Mar 24, 2009

Filed:

Feb 11, 2005

Appl. No.:

11/056894

Inventors:

Brian William Curran - Saugerties NY, US
Ashutosh Goyal - Austin TX, US
Michael Thomas Vaden - Austin TX, US
David Allan Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708490, 712226

Abstract:

A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

US Patent:

7676776, Mar 9, 2010

Filed:

Jun 25, 2007

Appl. No.:

11/767542

Inventors:

Giorgos Stellos Tsapepas - Poughkeepsie NY, US
David A. Webber - Poughkeepsie NY, US
Michael Hemsley Wood - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 17

Abstract:

A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.

US Patent:

7734944, Jun 8, 2010

Filed:

Jun 27, 2006

Appl. No.:

11/426648

Inventors:

Jonathan Y. Chen - Marlboro NY, US
Jeffrey A. Magee - Poughkeepsie NY, US
David A. Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 5/06
G06F 13/42
H04L 7/00

US Classification:

713400, 713401, 713600, 710305

Abstract:

A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

US Patent:

7735051, Jun 8, 2010

Filed:

Aug 29, 2006

Appl. No.:

11/468031

Inventors:

Gary A. Van Huben - Poughkeepsie NY, US
David A. Webber - Poughkeepsie NY, US
Christopher J. Berry - Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 18, 716 1, 716 17

Abstract:

Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.

US Patent:

7783911, Aug 24, 2010

Filed:

Jun 27, 2006

Appl. No.:

11/426666

Inventors:

Jonathan Y. Chen - Marlboro NY, US
Patrick J. Meaney - Poughkeepsie NY, US
Gary A. Van Huben - Poughkeepsie NY, US
David A. Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
G06F 13/42
H04L 7/00

US Classification:

713401, 713503, 375354

Abstract:

A double data rate elastic interface in which programmable latch stages provide an elastic delay, preferably on the driving side of the elastic interface. However, the invention is not limited to the driver side/chip, it can be implemented in the receiver side/chip as well. However, since the receiver side of an elastic interface already has complicated logic, the invention will be usually implemented on the driving side. The programmable latch stages on the driving chip side of the interface, can often operate at the local clock frequency (the same frequency as the elastic interface bus clock frequency), which in turn is half of the double data rate at which the receiving latch stages operate, thereby decreasing the logic and storage resources in the interface receivers. The programmable latch stages can also be used in the case that the local clock frequency is twice the elastic interface bus clock frequency.

US Patent:

7991816, Aug 2, 2011

Filed:

Aug 12, 2008

Appl. No.:

12/189797

Inventors:

Brian William Curran - Saugerties NY, US
Ashutosh Goyal - Austin TX, US
Michael Thomas Vaden - Austin TX, US
David Allan Webber - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38

US Classification:

708490, 708524

Abstract:

A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.