David L Wilstead

US Patent:

8065585, Nov 22, 2011

Filed:

Aug 30, 2007

Appl. No.:

11/897367

Inventors:

Ayyoob Abbaszadeh - Salt Lake City UT, US
David Todd Wilstead - West Valley UT, US

Assignee:

L-3 Communications Corporation - New York NY

International Classification:

H03M 13/00

US Classification:

714752

Abstract:

A source controller provides a block of n×a information bits as n separate rows each with a information bits. A row encoder has an input coupled to an output of the source controller and includes a plurality of accumulators arranged to process m of the information bits in one clock cycle to generate row forward error correction FEC bits. At least one column encoder has an input coupled to an output of the source controller and is arranged to generate column FEC bits in parallel with the row encoder. A multiplexer is coupled to outputs of the row and column encoders and is adapted to serially output an nrow of information bits followed by the nrow FEC bits for each of the n rows, followed by additional rows of FEC bits generated by the column encoder. The terms n, m, and a are integers greater than one. Where more than one column encoder is used, there are preferably m column encoders in parallel and each operating at one bit per clock cycle.