Disclosed is a circuit and method for multiple access of a branch history table during a single clock cycle. In accordance thereto, a first branch history table index is generated which is used for accessing the branch history table. A first counter value is read from the branch history table in response to accessing the branch history table using the first branch history table index. A second branch history table index is also generated for accessing the branch history table. A pair of counter values are read from the branch history table in response to accessing the branch history table using the second branch history table index. One of the pair of counter values is selected based upon the value of the first counter value read from the branch history table. The first and second counter values in turn are used for predicting corresponding first and second branch instructions. The first and second branch history table indexes are generated in the same cycle.
Processor Including Efficient Fetch Mechanism For L0 And L1 Caches
A processor employs a first instruction cache, a second instruction cache, and a fetch unit coupled to the first instruction cache and the second instruction cache. The fetch unit generates a branch target address responsive to a branch instruction which includes a displacement. Additionally, the fetch unit selects one of the first instruction cache and the second instruction cache from which to fetch instructions stored at the branch target address responsive to a size of the displacement.
Line-Oriented Reorder Buffer Configured To Selectively Store A Memory Operation Result In One Of The Plurality Of Reorder Buffer Storage Locations Corresponding To The Executed Instruction
A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.
Physical Rename Register For Efficiently Storing Floating Point, Integer, Condition Code, And Multimedia Values
David B. Witt - Austin TX James B. Keller - Palo Alto CA
Advanced Micro Devices, Inc. - Sunnyvale CA
712 36, 711210
A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e. g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e. g. floating point, integer, flags, etc. ), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource). By contrast, if different sets of physical registers are provided for different data types, only the physical registers used for the particular data type may be used for the aforementioned code sequence.
Instruction Alignment Unit For Routing Variable Byte-Length Instructions
An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instructions start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.
Hebbalalu S. Ramagopal - Austin TX David B. Witt - Austin TX Michael Allen - Austin TX Moinul Syed - Austin TX Ravi Kolagotla - Austin TX William C. Anderson - Austin TX
Intel Corporation - Santa Clara CA Analog Devices, Inc. - Norwood MA
711168, 711131, 711149, 711150, 711170
An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.
Processor Configured To Predecode Relative Control Transfer Instructions And Replace Displacements Therein With A Target Address
The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor. Additionally, the processor employs predecode information (stored in the instruction cache with the corresponding instruction bytes) including a start bit and a control transfer bit corresponding to each instruction byte.
Processor Including Efficient Fetch Mechanism For L0 And L1 Caches
A processor includes a first instruction cache, a second instruction cache, a return stack, and a fetch unit. The return stack is configured to store return addresses corresponding to call instructions. The return stack is configured to output a first return address from a top of the return stack and a second return address which is next to the top of the return stack. The fetch unit is coupled to the first instruction cache, the second instruction cache, and the return stack, and is configured to convey the first return address to the first instruction cache responsive to a return instruction. Additionally, the fetch unit is configured to convey the second return address to the second instruction cache responsive to the return instruction.
Yale Medical GroupSmilow Cancer Center Of Trumbull 5520 Park Ave FL 1, Trumbull, CT 06611 (203)5028400 (phone), (203)5028409 (fax)
Medical School New York University School of Medicine Graduated: 1978
Bone Marrow Biopsy Chemotherapy Electrocardiogram (EKG or ECG) Vaccine Administration
Anemia Hemolytic Anemia Iron Deficiency Anemia Leukemia Multiple Myeloma
Dr. Witt graduated from the New York University School of Medicine in 1978. He works in Trumbull, CT and specializes in Hematology/Oncology. Dr. Witt is affiliated with Bridgeport Hospital, St Vincents Medical Center and Yale New Haven Hospital.
Kaiser Permanente Medical Group 97 San Marin Dr, Novato, CA 94945 (415)8997400 (phone), (415)8997506 (fax)
Medical School University of Michigan Medical School Graduated: 1979
English Spanish Tagalog
Dr. Witt graduated from the University of Michigan Medical School in 1979. He works in Novato, CA and specializes in Infectious Disease. Dr. Witt is affiliated with Kaiser Permanente Santa Clara Medical Center.
Dr. Witt graduated from the University of Texas Medical School at Houston in 1997. He works in Longview, TX and specializes in Family Medicine. Dr. Witt is affiliated with Longview Regional Medical Center.
Fisher had sailed with Scallywag skipper David Witt for years on the Ragamuffin and Scallywag super maxis and had lived in Southampton; more recently, he was based in Adelaide, Australia. The teams website describes him as having plenty of big boat experience and said he is a veteran of the Sydne
2017-18 Edition: Entered Teams Skippers Team AkzoNobel (NED), Simeon Tienpont (NED) Dongfeng Race Team (CHN), Charles Caudrelier (FRA) MAPFRE (ESP), Xabi Fernndez (ESP) Vestas 11th Hour Racing (DEN/USA), Charlie Enright (USA) Team Sun Hung Kai/Scallywag (HKG), David Witt (AUS) Turn th
Date: Mar 27, 2018
After best Wimbledon since '09, Venus Williams vows return
''I just think it was a missed opportunity here,'' said Venus' coach, David Witt. ''She could've easily been in the finals, and then in the finals, all it takes is one good match of unbelievable tennis and you just don't know what happens.''
Date: Jul 08, 2016
Venus, Serena Williams 1 win apiece from Wimbledon final
"It's nice to see, because she puts in the work," said David Witt, Williams' coach. "She hasn't been back, but not because of her play. Any given tournament, she's capable of beating anybody in the tournament. It's just a matter of winning six, seven matches in a row and keeping your level of play a
Her coach, David Witt, says Venus remains resolute enough to believe she can still win the title here and even play for several more years. Patrick Mouratoglou, Serena's coach, says "there's never been any retirement" talk among the sisters in his presence.
Venus has been working with her coach, David Witt, since a little over forever, as she might saythey started hitting together back in 2002.In her approach and dedication to her profession, Venus seems to have changed little over the years. Shes still as stoic in defeat and delighted in v
"The real reason we fear it is that it kills young infants," said Dr. David Witt, an infectious disease specialist at Kaiser Permanente San Rafael. "In adults, it can be extremely annoying - one translation of the Chinese name for it is the 'hundred days cough,' for perspective. [But] in young infan