David R Witt

US Patent:

6347369, Feb 12, 2002

Filed:

Sep 24, 1998

Appl. No.:

09/159900

Inventors:

David B. Witt - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 940

US Classification:

712240

Abstract:

Disclosed is a circuit and method for multiple access of a branch history table during a single clock cycle. In accordance thereto, a first branch history table index is generated which is used for accessing the branch history table. A first counter value is read from the branch history table in response to accessing the branch history table using the first branch history table index. A second branch history table index is also generated for accessing the branch history table. A pair of counter values are read from the branch history table in response to accessing the branch history table using the second branch history table index. One of the pair of counter values is selected based upon the value of the first counter value read from the branch history table. The first and second counter values in turn are used for predicting corresponding first and second branch instructions. The first and second branch history table indexes are generated in the same cycle.

US Patent:

6367001, Apr 2, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/735197

Inventors:

David B. Witt - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 932

US Classification:

712205, 711122, 712207, 712237

Abstract:

A processor employs a first instruction cache, a second instruction cache, and a fetch unit coupled to the first instruction cache and the second instruction cache. The fetch unit generates a branch target address responsive to a branch instruction which includes a displacement. Additionally, the fetch unit selects one of the first instruction cache and the second instruction cache from which to fetch instructions stored at the branch target address responsive to a size of the displacement.

US Patent:

6381689, Apr 30, 2002

Filed:

Mar 13, 2001

Appl. No.:

09/804768

Inventors:

David B. Witt - Austin TX
Thang M. Tran - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1500

US Classification:

712215, 712 23, 712212, 712213, 712216, 712217, 712218, 712214, 712222, 712235

Abstract:

A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor.

US Patent:

6393546, May 21, 2002

Filed:

Feb 16, 2001

Appl. No.:

09/788067

Inventors:

David B. Witt - Austin TX
James B. Keller - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1202

US Classification:

712 36, 711210

Abstract:

A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e. g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e. g. floating point, integer, flags, etc. ), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource). By contrast, if different sets of physical registers are provided for different data types, only the physical registers used for the particular data type may be used for the aforementioned code sequence.

US Patent:

6393549, May 21, 2002

Filed:

Dec 21, 1999

Appl. No.:

09/468693

Inventors:

Thang Tran - Austin TX
David B. Witt - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 930

US Classification:

712204, 712215

Abstract:

An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instructions start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.

US Patent:

6446181, Sep 3, 2002

Filed:

Mar 31, 2000

Appl. No.:

09/541117

Inventors:

Hebbalalu S. Ramagopal - Austin TX
David B. Witt - Austin TX
Michael Allen - Austin TX
Moinul Syed - Austin TX
Ravi Kolagotla - Austin TX
William C. Anderson - Austin TX

Assignee:

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1200

US Classification:

711168, 711131, 711149, 711150, 711170

Abstract:

An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.

US Patent:

6457117, Sep 24, 2002

Filed:

Nov 7, 2000

Appl. No.:

09/708216

Inventors:

David B. Witt - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9312

US Classification:

712213, 712204, 712206, 712207, 712211, 712227, 712235, 712237, 712239

Abstract:

The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor. Additionally, the processor employs predecode information (stored in the instruction cache with the corresponding instruction bytes) including a start bit and a control transfer bit corresponding to each instruction byte.

US Patent:

6505292, Jan 7, 2003

Filed:

Jan 29, 2002

Appl. No.:

10/059713

Inventors:

David B. Witt - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 938

US Classification:

712207, 711122, 711213, 712237, 712238

Abstract:

A processor includes a first instruction cache, a second instruction cache, a return stack, and a fetch unit. The return stack is configured to store return addresses corresponding to call instructions. The return stack is configured to output a first return address from a top of the return stack and a second return address which is next to the top of the return stack. The fetch unit is coupled to the first instruction cache, the second instruction cache, and the return stack, and is configured to convey the first return address to the first instruction cache responsive to a return instruction. Additionally, the fetch unit is configured to convey the second return address to the second instruction cache responsive to the return instruction.

Address:

341 Kingsbridge Dr, Garland, TX 75040

Phone:

(469)6282660

VIN:

1C4RJFAG7CC284507

Make:

JEEP

Model:

GRAND CHEROKEE

Year:

2012