Deborah Kelsey Marr

US Patent:

20180165381, Jun 14, 2018

Filed:

Dec 12, 2016

Appl. No.:

15/376172

Inventors:

- Santa Clara CA, US
Nicholas P. Carter - SOMERVILLE MA, US
Deborah T. Marr - Portland OR, US

International Classification:

G06F 17/30

Abstract:

A processor may include a gather-update-scatter accelerator, and circuitry to direct an instruction to the accelerator for execution. The instruction may include a search index, an operation to be performed, and a scalar data value. The accelerator may include a content-associative memory (CAM) storing multiple entries, each of which stores a respective index key and a data value associated with the index key. The accelerator may include a CAM controller, including circuitry to select, based on the information in the instruction, one of the plurality of entries in the CAM on which to operate, an arithmetic logic unit (ALU), including circuitry to perform an arithmetic or logical operation on the selected entry, the operation being dependent on the information in the instruction, and circuitry to store a result of the operation in the selected entry in the CAM.