Deli Wang

US Patent:

8426224, Apr 23, 2013

Filed:

Dec 18, 2007

Appl. No.:

12/520082

Inventors:

Deli Wang - San Diego CA, US
Xinyu Bao - Mountain View CA, US
Bin Xiang - El Cerrito CA, US
Cesare Soci - San Diego CA, US
David Aplin - La Jolla CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 21/00

US Classification:

438 22, 136263, 977762

Abstract:

Semiconductor nanowire arrays are used to replace the conventional planar layered construction for fabrication of LEDs and laser diodes. The nanowire arrays are formed from III-V or II-VI compound semiconductors on a conducting substrate. For fabrication of the device, an electrode layer is deposited on the substrate, a core material of one of a p-type and n-type compound semiconductor material is formed on top of the electrode as a planar base with a plurality of nanowires extending substantially vertically therefrom. A shell material of the other of the p-type and n-type compound semiconductor material is formed over an outer surface of the core material so that a p-n junction is formed across the planar base and over each of the plurality of nanowires. An electrode coating is formed an outer surface of the shell material for providing electrical contact to a current source. Heterostructures and superlattices grown along the lengths of the nanowires allow the confinement of photons in the quantum well to enhance the efficiency and as well as color tuning.

US Patent:

8440997, May 14, 2013

Filed:

Feb 26, 2008

Appl. No.:

12/528701

Inventors:

Deli Wang - San Diego CA, US
Cesare Soci - La Jolla CA, US
Yu-Hwa Lo - San Diego CA, US
Arthur Zhang - San Diego CA, US
David Aplin - Wisbech, GB
Lingquan Wang - Santa Clara CA, US
Shadi Dayeh - Los Alamos NM, US
Xin Yu Bao - Mountain View CA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01L 29/06

US Classification:

257 21, 257130, 257368, 257E29245, 438 3, 438364, 438478, 438660

Abstract:

A 1D nanowire photodetector device includes a nanowire that is individually contacted by electrodes for applying a longitudinal electric field which drives the photocurrent. An intrinsic radial electric field to inhibits photo-carrier recombination, thus enhancing the photocurrent response. Circuits of 1D nanowire include groups of photodetectors addressed by their individual 1D nanowire electrode contacts. Placement of 1D nanostructures is accomplished with registration onto a substrate. A substrate is patterned with a material, e. g. , photoresist, and trenches are formed in the patterning material at predetermined locations for the placement of 1D nanostructures. The 1D nanostructures are aligned in a liquid suspension, and then transferred into the trenches from the liquid suspension. Removal of the patterning material places the 1D nanostructures in predetermined, registered positions on the substrate.

US Patent:

20030089899, May 15, 2003

Filed:

Jul 16, 2002

Appl. No.:

10/196337

Inventors:

Charles Lieber - Lexington MA, US
Xiangfeng Duan - Somerville MA, US
Yi Cui - Union City CA, US
Yu Huang - Cambridge MA, US
Mark Gudiksen - Watertown MA, US
Lincoln Lauhon - Boston MA, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Somerville MA, US
David Smith - Midanbury, GB
Deli Wang - Cambridge MA, US
Zhaohui Zhong - Cambridge MA, US

International Classification:

H01L029/06

US Classification:

257/009000

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

20060175601, Aug 10, 2006

Filed:

Jun 30, 2005

Appl. No.:

11/172408

Inventors:

Charles Lieber - Lexington MA, US
Xiangfeng Duan - Mountain View MA, US
Yi Cui - Union City CA, US
Yu Huang - Cambridge MA, US
Mark Gudiksen - Castro Valley CA, US
Lincoln Lauhon - Chicago IL, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Somerville MA, US
David Smith - Reading, GB
Deli Wang - San Diego CA, US
Zhaohui Zhong - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 31/109

US Classification:

257019000

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

20070281156, Dec 6, 2007

Filed:

Mar 21, 2006

Appl. No.:

11/386080

Inventors:

Charles Lieber - Lexington MA, US
Xiangfeng Duan - Mountain View CA, US
Yi Cui - Union City CA, US
Yu Huang - Cambridge MA, US
Mark Gudiksen - Castro Valley CA, US
Lincoln Lauhon - Chicago IL, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Somerville MA, US
David Smith - Reading, GB
Deli Wang - San Diego CA, US
Zhaohui Zhong - Cambridge MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

D02G 3/00

US Classification:

428373000, 428401000

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

20090057650, Mar 5, 2009

Filed:

Feb 27, 2008

Appl. No.:

12/072844

Inventors:

Charles M. Lieber - Lexington MA, US
Xiangfeng Duan - Los Angeles CA, US
Yi Cui - Sunnyvale CA, US
Yu Huang - Los Angeles CA, US
Mark Gudiksen - Castro Valley CA, US
Lincoln J. Lauhon - Chicago IL, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Oakland CA, US
David C. Smith - Reading, GB
Deli Wang - San Diego CA, US
Zhaohui Zhong - Ithaca NY, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 29/66

US Classification:

257 24, 257E29168, 977762

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

20100155698, Jun 24, 2010

Filed:

Jun 26, 2009

Appl. No.:

12/459177

Inventors:

Charles M. Lieber - Lexington MA, US
Xiangfeng Duan - Los Angeles CA, US
Yi Cui - Sunnyvale CA, US
Yu Huang - Los Angeles CA, US
Mark Gudiksen - Castro Valley CA, US
Lincoln J. Lauhon - Chicago IL, US
Jianfang Wang - Goleta CA, US
Hongkun Park - Lexington MA, US
Qingqiao Wei - Corvallis OR, US
Wenjie Liang - Oakland CA, US
David C. Smith - Reading, GB
Deli Wang - San Diego CA, US
Zhaohui Zhong - Ithaca NY, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 29/12
H01L 21/20

US Classification:

257 14, 438478, 257E2907, 257E2109, 977762

Abstract:

The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

US Patent:

20110253982, Oct 20, 2011

Filed:

Oct 28, 2009

Appl. No.:

13/126381

Inventors:

Deli Wang - San Diego CA, US
Cesare Soci - San Diego CA, US
Xinyu Bao - San Diego CA, US
Wei Wei - La Jolla CA, US
Yi Jing - La Jolla CA, US
Ke Sun - La Jolla CA, US

Assignee:

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA - Oakland CA

International Classification:

H01L 29/775
H01L 21/20
H01L 29/66
B82Y 99/00
B82Y 40/00

US Classification:

257 24, 438504, 257 14, 257E2109, 257E29168, 257E29245, 977762, 977938

Abstract:

Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.