Dennis A Robinson

US Patent:

54504171, Sep 12, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/149243

Inventors:

Phat C. Truong - Houston TX
Tim M. Coffman - Sugar Land TX
T. Damodar Reddy - Nalgonda, IN
Dennis R. Robinson - Needville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 1700

US Classification:

371 221

Abstract:

The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

US Patent:

51209993, Jun 9, 1992

Filed:

Feb 8, 1991

Appl. No.:

7/652755

Inventors:

John F. Schreck - Houston TX
Dennis R. Robinson - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1716
H03K 19094

US Classification:

307443

Abstract:

Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise. In one form the output buffer circuit comprises a NOR circuit having a first input coupled to a data input and a second input to an enable input, a NAND circuit having a first input coupled to the data input and a second input coupled to an enable input, a first inverter transistor pair having gates coupled to the output of the NOR circuit and having source-drain paths in series coupled to a reference, a second inverter transistor pair having gates coupled to the output of the NAND circuit and having source-drain paths coupled in series to a supply, a resistor coupled between in series between the source-drain paths of the first transistor pair and the supply, a resistor coupled in series between the second transistor pair and the reference, and a third inverter transistor pair with each gate of the third transistor pair coupled to one of the outputs of the first and second inverter transistor pairs and with the output of the third transistor pair coupled to the output of the buffer circuit.

US Patent:

53961153, Mar 7, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/149245

Inventors:

Tim M. Coffman - Sugar Land TX
Phat C. Truong - Houston TX
T. Damodar Reddy - Nalgonda, IN
Dennis R. Robinson - Needville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1722

US Classification:

327143

Abstract:

The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

US Patent:

53979460, Mar 14, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/149246

Inventors:

Phat C. Truong - Houston TX
Tim M. Coffman - Sugar Land TX
T. Damodar Reddy - Nalgonda, IN
Dennis R. Robinson - Needville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3193
G11C 700

US Classification:

327 74

Abstract:

The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

US Patent:

53922484, Feb 21, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/149242

Inventors:

Phat C. Truong - Houston TX
Tim M. Coffman - Sugar Land TX
T. Damodar Reddy - Nalgonda, IN
Dennis R. Robinson - Needville TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

365201

Abstract:

The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.

US Patent:

54249929, Jun 13, 1995

Filed:

Aug 25, 1993

Appl. No.:

8/112484

Inventors:

Tim M. Coffman - Sugar Land TX
Dennis R. Robinson - Needville TX
Phat C. Truong - Houston TX
T. Damodar Reddy - Nalgonda, IN

Assignee:

Texas Instruments Incorporated, a Delaware corporation - Dallas TX

International Classification:

G11C 1300

US Classification:

365218

Abstract:

An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL. sub. --). The higher voltage level bias signal (ECL. sub. --) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM. sub. --) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM. sub. --) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.