Derek Freeman Davis

US Patent:

6357004, Mar 12, 2002

Filed:

Sep 30, 1997

Appl. No.:

08/940231

Inventors:

Derek L. Davis - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1130

US Classification:

713100, 713176

Abstract:

The system and method to protect integrity of a data set during post-processing operations. In general, integrity is protected by operations performed by a manipulation agent including a processor connected to dedicated memory. The operations of the manipulation agent include at least providing a data set and recording characteristics of each post-processing operation into the data set. The data set includes data and a record. The record includes a number of entries (fields) to contain the various characteristics of a post-processing operation such as an incoming hash value of the data, an extended digital signature, and the like.

US Patent:

6389533, May 14, 2002

Filed:

Feb 5, 1999

Appl. No.:

09/244803

Inventors:

Derek L. Davis - Phoenix AZ
Jean-Charles Korta - Mesa AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 900

US Classification:

713162, 713153, 713154, 713151

Abstract:

An anonymity system including a cryptographic device. The cryptographic device of the anonymity system is adapted to initially determine whether a response to an incoming electronic message is requested. If so, an address of the anonymity system is encrypted with a key. In one embodiment, the key may be a public key of a system targeted to receive an outgoing electronic message from the anonymity system inclusive of data contained in the incoming electronic message. The encrypted address is placed into an outgoing electronic message before re-routing to the target system to allow the target system to re-route the response back to the anonymity system.

US Patent:

6389537, May 14, 2002

Filed:

Apr 23, 1999

Appl. No.:

09/298360

Inventors:

Derek L. Davis - Phoenix AZ
Howard C. Herbert - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 932

US Classification:

713187

Abstract:

A cryptographic device comprising a processing logic and memory associated with the processing logic. The memory is loaded with a first segment of code to control execution of cryptographic functions and hash functions, and a second segment of code to perform cryptographic functions on behalf of a third party having no physical control of hardware employing the cryptographic device.

US Patent:

6401208, Jun 4, 2002

Filed:

Jul 17, 1998

Appl. No.:

09/118147

Inventors:

Derek L. Davis - Phoenix AZ
Pranav Mehta - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 932

US Classification:

713193, 713189, 713188, 713187, 713191

Abstract:

A cryptographic device is implemented in communication with a host processor to prevent the host processor from performing a standard boot-up procedure until a basic input output system (BIOS) code is authenticated. This is accomplished by a cryptographic device which is addressed by the host processor during execution of a first instruction following a power-up reset. The cryptographic device includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a memory to contain firmware and a root certification key. The second IC device includes logic circuitry to execute a software code to authenticate the BIOS code before permitting execution of the BIOS code by the host processor.

US Patent:

6629244, Sep 30, 2003

Filed:

Nov 16, 2001

Appl. No.:

09/995994

Inventors:

Derek L. Davis - Phoenix AZ
Howard C. Herbert - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1130

US Classification:

713187, 713201

Abstract:

A cryptographic device comprising a processing logic and memory associated with the processing logic. The memory is loaded with a first segment of code to control execution of cryptographic functions and hash functions, and a second segment of code to perform cryptographic functions on behalf of a third party having no physical control of hardware employing the cryptographic device.

US Patent:

6633981, Oct 14, 2003

Filed:

Jun 18, 1999

Appl. No.:

09/336009

Inventors:

Derek L. Davis - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 0124

US Classification:

713189, 713155, 713159, 713182, 713185

Abstract:

A Basic Input/Output System (BIOS) device is designed to control access to a portion of BIOS code loaded in its internal memory. For example, during a boot process, an internal state machine permits access to the portion of the BIOS code in response to authentication of a portable token in communication with the BIOS device. Otherwise, the BIOS device precludes access to the portion of the BIOS code until the portable token is authenticated.

US Patent:

6708274, Mar 16, 2004

Filed:

Apr 30, 1998

Appl. No.:

09/071374

Inventors:

Howard C. Herbert - Phoenix AZ
Derek L. Davis - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 906

US Classification:

713190, 713177, 713189, 713193, 713194, 713200, 713201, 380 25, 380 30

Abstract:

A method and system for maintaining integrity and confidentiality of pages paged to an external storage unit from a physically secure environment. An outgoing page is selected to be exported from a physically secure environment to an insecure environment. An integrity check value is generated and stored for the outgoing page. In one embodiment, this takes the form of taking a one-way hash of the page using a well-known one-way hash function. The outgoing page is then encrypted using a cryptographically strong encryption algorithm. Among the algorithms that might be used in one embodiment of the invention are IDEA and DES. The encrypted outgoing page is then exported to the external storage. By virtue of the encryption and integrity check, the security of the data on the outgoing page is maintained in the insecure environment.

US Patent:

6775770, Aug 10, 2004

Filed:

Dec 30, 1999

Appl. No.:

09/476059

Inventors:

Derek L. Davis - Phoenix AZ
Shawn C. Beckman - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 900

US Classification:

713156, 713168, 713175, 713176

Abstract:

A platform and a corresponding method for protecting the integrity of data transferred between the user input device and a secure processing unit. In one embodiment, this can be accomplished by establishing a virtual secure path between a device controller of the user input device and the secure processing unit. Thereafter, when sensitive information is input by the user via the user input device, the device controller is placed in a first mode of operation to securely transfer the sensitive information from the user input device to the secure processing unit over the virtual secure path. Additionally, a security indicator is placed in an Active state to indicate to the user that the sensitive information is being securely transferred to the secure processing unit.