Dev Datta

US Patent:

7512695, Mar 31, 2009

Filed:

May 7, 2003

Appl. No.:

10/431973

Inventors:

Mohamed Magdy Talaat - San Jose CA, US
Rick Reeve - San Francisco CA, US
Richard L. Schober - Cupertino CA, US
Prasad Vajjhala - San Jose CA, US
Yolin Lih - San Jose CA, US
Dev Datta - Fremont CA, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

G06F 15/16

US Classification:

709230, 709224, 3703955, 370464, 370469, 710315, 710105

Abstract:

A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the identification component at the destination interconnect device. The identification component is then processed at the destination interconnect device, the identification component relating to the contents of the data. The invention extends to a machine-readable medium embodying a set of instructions for executing the method and to an interconnect device.

US Patent:

6393572, May 21, 2002

Filed:

Apr 28, 1999

Appl. No.:

09/300902

Inventors:

Dev Datta - Fremont CA
Rune H. Jensen - Sunnyvale CA
Calto Wong - Sunnyvale CA
Daisuke Takise - San Jose CA

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

G06F 132

US Classification:

713322, 713601

Abstract:

In a master-slave configuration wherein a sleepmode activation is effected by the cessation of a clocking signal, the need for an analog device or auxiliary clock for detecting the cessation of the clocking signal is obviated by anticipating the cessation of the clock signal. Upon anticipating the cessation of the clock signal, the remaining clock signaling before cessation is used as required to effect a controlled power-down of the slave device. By eliminating the need for an analog clock cessation detector, the process tolerance constraints associated with analog circuitry can be avoided, the reliability and robustness of the design is improved, and the required testing is simplified, thereby reducing the cost of the device. In like manner, the elimination of an auxiliary clock generator reduces the cost and complexity of the device and system, and improves the device and systems overall reliability and testability. In accordance with this invention, the anticipation of the cessation of the clock signal is achieved by monitoring the communications among devices for commands that can be expected to affect the generation of the clock signal.