Devendra Sheethal Kumar

US Patent:

6423947, Jul 23, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/896525

Inventors:

Jeffrey D. Womack - Pleasanton CA
Vuong P. Nguyen - San Jose CA
Devendra Kumar - Los Altos CA
Jack S. Kasahara - Los Gatos CA
Sokol Ibrani - Pleasanton CA

Assignee:

FSI International, Inc. - Chaska MN

International Classification:

H05B 514

US Classification:

219390, 219405, 219411, 392416, 118724, 118725

Abstract:

A processing chamber and methods for employing this processing chamber to thermally treat wafer-like objects. The chamber comprises a double walled shell, a pedestal style heater, internal passages for the transport of cooling gases and removal of exhaust gases, independently variable gas introduction patterns, and a movable door for sealing the chamber. The chamber is designed to permit in situ cooling of wafer-like objects and to provide means for precise optimization of this cooling. The methods provide for the processing of the wafer-like object in an environment where the temperature, rate of change of the temperature, composition of gases and the relative timings of changes to these variables may be controlled to achieve the desired material properties in the wafer-like object or in films contained on this wafer-like object.

US Patent:

6838115, Jan 4, 2005

Filed:

Jul 11, 2001

Appl. No.:

09/903114

Inventors:

Devendra Kumar - Los Altos CA, US
Jeffrey D. Womack - Lake Oswego OR, US
Vuong P. Nguyen - Allen TX, US
Jack S. Kasahara - Los Gatos CA, US
Sokol Ibrani - Pleasanton CA, US

Assignee:

FSI International, Inc. - Chaska MN

International Classification:

B05D 512
B05D 302

US Classification:

427 58, 427240, 4273722, 4273741, 427379, 4273855, 4273984, 427350

Abstract:

Single wafer processing methods and systems for manufacturing films having low-k properties and low indices of refraction. The methods incorporate a processing station in which both curing and post-cure, in situ gas cooling take place.

US Patent:

6881683, Apr 19, 2005

Filed:

Dec 11, 2002

Appl. No.:

10/317239

Inventors:

Nobuo Matsuki - Tami, JP
Yasuyoshi Hyodo - Tami, JP
Masashi Yamaguchi - Tami, JP
Yoshinori Morisada - Tami, JP
Atsuki Fukazawa - Tami, JP
Manabu Kato - Tami, JP
Shinya Kaneko - Tami, JP
Devendra Kumar - Los Altos CA, US
Seijiro Umemoto - Tami, JP

Assignee:

ASM Japan K.K. - Tokyo

International Classification:

H01L021/469

US Classification:

438789, 438758, 438788, 438790

Abstract:

An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus. The silicon-containing hydrocarbon compound includes a cyclosiloxan compound or a linear siloxan compound, as a basal structure, with reactive groups for form oligomers using the basal structure. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.

US Patent:

6949456, Sep 27, 2005

Filed:

Oct 24, 2003

Appl. No.:

10/693200

Inventors:

Devendra Kumar - Los Altos CA, US

Assignee:

ASM Japan K.K. - Tokyo

International Classification:

H01L021/4763

US Classification:

438619, 438623, 257522, 257762, 257759

Abstract:

A method for manufacturing a semiconductor device includes: (i) depositing a sacrificial layer made of an organic polymer such as benzocyclobutene on a substrate having a circuit formed thereon; (ii) etching the sacrificial layer except for a portion where air gaps are to be formed; (iii) depositing a low-dielectric layer over the substrate until the portion for air gaps is entirely enclosed in the low-dielectric layer; (iv) etching the low-dielectric layer to form via holes and trenches there through; (v) prior or subsequent to step (iv), removing the portion for air gaps; and (vi) depositing copper in the vias and trenches which are filled with the copper contacting a surface of the substrate.

US Patent:

7498242, Mar 3, 2009

Filed:

Feb 21, 2006

Appl. No.:

11/359884

Inventors:

Devendra Kumar - Los Altos Hills CA, US
Kamal Kishore Goundar - Yokohama, JP
Nathanael R. C. Kemeling - Lightheim, JP
Hideaki Fukuda - Tama, JP
Hessel Sprey - Kessel-Lo, BE
Maarten Stokhof - Leuven, BE

Assignee:

ASM America, Inc. - Phoenix AZ

International Classification:

H01L 21/322

US Classification:

438474, 438687, 438798, 438FOR 117, 438FOR 447, 257762, 257E21627, 257E21641

Abstract:

Method and structures are provided for conformal lining of dual damascene structures in integrated circuits. Preferred embodiments are directed to providing conformal lining over openings formed in porous materials. Trenches are formed in, preferably, insulating layers. The layers are then adequately treated with a particular plasma process. Following this plasma treatment a self-limiting, self-saturating atomic layer deposition (ALD) reaction can occur without significantly filling the pores forming improved interconnects.

US Patent:

20040047993, Mar 11, 2004

Filed:

Sep 5, 2003

Appl. No.:

10/656640

Inventors:

Devendra Kumar - Los Altos CA, US
Jeffrey Womack - Lake Oswego OR, US
Vuong Nguyen - Allen TX, US
Jack Kasahara - Los Gatos CA, US
Sokol Ibrani - Pleasanton CA, US

International Classification:

B05D003/12
B05D003/02
B32B031/00

US Classification:

427/294000, 427/374100, 427/372200, 427/350000, 156/272200, 156/273300, 118/300000

Abstract:

Single wafer processing methods and systems for manufacturing films having low-k properties and low indices of refraction. The methods incorporate a processing station in which both curing and post-cure, in situ gas cooling take place.

US Patent:

20050179135, Aug 18, 2005

Filed:

Apr 13, 2005

Appl. No.:

11/105250

Inventors:

Devendra Kumar - Los Altos CA, US

Assignee:

ASM Japan K.K. - Tokyo

International Classification:

H01L029/02
H01L023/48

US Classification:

257758000, 438619000

Abstract:

A semiconductor device having a hollow structure includes: a substrate on which a wiring layer is formed; a low-dielectric layer with a porosity of 6% to 25% having vias and trenches and having voids between adjacent vias; and a contact layer of copper with which the vias and trenches are filled. The contact layer is in contact with the wiring layer and an upper surface of the contact layer is exposed from the dielectric layer.

US Patent:

20060151002, Jul 13, 2006

Filed:

Dec 22, 2004

Appl. No.:

11/022083

Inventors:

Devendra Kumar - Los Altos Hills CA, US

International Classification:

B08B 6/00
B08B 9/00
H05H 1/24

US Classification:

134001100, 134022100, 427569000

Abstract:

A method for cleaning a plasma CVD reactor includes, during a cleaning cycle, (i) providing cleaning active species derived from a cleaning gas in the plasma CVD reactor, and (ii) generating a hydrogen plasma in an interior of the plasma CVD reactor to clean the interior of the reactor.