Dexter T Chun

US Patent:

7061804, Jun 13, 2006

Filed:

Nov 18, 2004

Appl. No.:

10/993034

Inventors:

Dexter Tamio Chun - San Diego CA, US
Ajit Patil - San Diego CA, US
Ian Huang - San Diego CA, US
Jason Chan - San Diego CA, US
Timothy Gold - Ramona CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G11C 11/34

US Classification:

36518517, 3652385

Abstract:

Techniques for quickly and reliably accessing a memory device (e. g. , a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

US Patent:

7092409, Aug 15, 2006

Filed:

Mar 21, 2001

Appl. No.:

09/814658

Inventors:

Dexter Chun - San Diego CA, US
Steve Hicks - San Diego CA, US
Bob Knight - San Diego CA, US
KC Lee - San Diego CA, US
Ravi Palakodety - San Diego CA, US
Dave Walker - Escondido CA, US
Jun Zhang - San Diego CA, US

Assignee:

Telefonaktiebolaget LM Ericsson (publ)

International Classification:

H04L 12/42

US Classification:

370507

Abstract:

A timing network for a wireless communication network includes first and second Timing Unit Board (TUB) and processor boards for processing speech channels of the radio network, each processor board having a local timer that is slave to “PSTN time” from a Public Switch Telephone Network (PSTN). The first and second TUB each alternately transmits a timing cell containing time information to each processor board over a transport network. Each processor board realigns its local timer with the time information contained in a received timing cell whenever its local timer drifts from the time information contained in the received timing cell by a predetermined time offset. When one of the TUBs fails to transmit timing cells to the processor boards or transmits timing cells containing erroneous time information, the processor boards rely on the remaining TUB for timing cells to realign their local timers.

US Patent:

8291226, Oct 16, 2012

Filed:

Feb 10, 2006

Appl. No.:

11/351966

Inventors:

Dexter Tamio Chun - San Diego CA, US
Ajit B. Patil - San Diego CA, US
Cuneyt Fitoz - San Diego CA, US
Dwight Gordon - San Diego CA, US
Yu-Hsiang Huang - San Diego CA, US
Oliver Michaelis - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04L 9/32
H04L 29/06
G06F 7/04
G06F 13/00
H04K 1/00
H04L 9/00
G06F 9/44
G06F 9/24

US Classification:

713176, 726 27, 711103, 713164

Abstract:

Techniques to securely boot up an electronics device (e. g. , a cellular phone) from an external storage device are described. Secure data (e. g. , a hash digest, a signature, a cryptographic key, and so on) is initially retrieved from a non-writable area of an external memory device (e. g. , an one-time programmable (OTP) area of a NAND Flash device). A first program (e. g. , a boot program) is retrieved from a writable or main area of the external memory device and authenticated based on the secure data. The first program is enabled for execution if authenticated. A second program may be retrieved from the main area of the external memory device and authenticated based on the secure data. The second program is enabled for execution if authenticated. Additional programs may be retrieved and authenticated.

US Patent:

8578222, Nov 5, 2013

Filed:

Feb 17, 2011

Appl. No.:

13/029934

Inventors:

Dexter T Chun - San Diego CA, US
Jack K Wolf - San Diego CA, US
Jungwon Suh - San Diego CA, US
Tirdad Sowlati - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

G06F 11/00

US Classification:

714708, 714704

Abstract:

A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.

US Patent:

7269181, Sep 11, 2007

Filed:

Apr 4, 2001

Appl. No.:

09/826224

Inventors:

Dexter Chun - San Diego CA, US
Robert Knight - San Diego CA, US
Ravi Palakodety - San Diego CA, US

Assignee:

Telefonaktiebolaget LM Ericsson (publ)

International Classification:

H04M 1/00
H04B 7/00

US Classification:

370422, 370218, 3703951, 455569

Abstract:

A base station controller system comprises a high data rate distributed switching fabric providing flexible access to call processing resource pools. The arrangement permits a system controller to selectively assign specific resources depending on call type based on configuring the distributed switching fabric. The transport links comprising the distributed switching fabric provide redundant access to each of the resource pools, greatly reducing the portion of overall call processing capability lost with a single failure. Preferably, the distributed switching fabric comprises a central ATM switch and a number of distributed ATM switches interconnecting the resource pools to the central switching resource. The system may adopt a rack arrangement wherein a processing subrack includes the mix of different processing resources necessary to support substantially all call flow processing for one or more types of calls. The system's call capacity is thus easily scalable based on adding additional processing subracks.

US Patent:

20050114725, May 26, 2005

Filed:

Nov 25, 2003

Appl. No.:

10/722350

Inventors:

Jagrut Patel - San Diego CA, US
Dexter Chun - San Diego CA, US
Gregory Bullard - La Mesa CA, US
Raghu Sankuratri - San Diego CA, US
Rajeev Prabhakaran - San Diego CA, US
Sanat Kapoor - San Diego CA, US

International Classification:

G06F001/04

US Classification:

713500000

Abstract:

Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.

US Patent:

20130271920, Oct 17, 2013

Filed:

Apr 12, 2012

Appl. No.:

13/445385

Inventors:

Dexter T. Chun - San Diego CA, US
Victor A. Chiriac - San Diego CA, US
James H. Thompson - San Diego CA, US
Stephen A. Molloy - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H05K 7/20
B23P 19/04
F28F 7/00

US Classification:

361705, 361714, 165185, 29428

Abstract:

Electronic devices incorporating a heat dissipation feature include an enclosure, and at least one heat-generating component positioned within the enclosure. The heat dissipation feature is sufficiently coupled to the at least one heat-generating component to facilitate conductive heat transfer from the heat-generating component. The heat dissipation feature includes a plurality of protrusions exposed externally to the enclosure. A thermally insulating material may be disposed on at least a tip portion of at least some of the protrusions. The thermally insulating material is selected to provide a touch temperature that is below a predetermined threshold. In some instances, the thermally insulating material can provide such a touch temperature by selecting the material to include properties for thermal conductivity (k), density (ρ), and specific heat (C) such that the product of k*ρ*Cresults in a value less than a product of k*ρ*Cfor human skin.

US Patent:

20130326188, Dec 5, 2013

Filed:

Jan 29, 2013

Appl. No.:

13/752427

Inventors:

Dexter T. Chun - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

G06F 12/10

US Classification:

711206

Abstract:

In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.