Dominic William Mccarthy

US Patent:

6549446, Apr 15, 2003

Filed:

Jan 25, 2002

Appl. No.:

09/959591

Inventors:

Stephen Morley - Bristol, GB
Kevin Lloyd-Jones - Bristol, GB
Dominic P. McCarthy - Mountain View CA
Peter Joseph Bramhall - Bristol, GB

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G11C 1702

US Classification:

365 97, 3652255

Abstract:

A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of â1âs and â0âs, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the â1âs and â0âs are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

US Patent:

6708282, Mar 16, 2004

Filed:

Sep 5, 2000

Appl. No.:

09/654759

Inventors:

Dominic Paul McCarthy - Los Altos CA
Jack Choquette - Mountain View CA

Assignee:

Raza Microelectronics, Inc. - San Jose CA

International Classification:

G06F 1342

US Classification:

713400, 713502, 712 32

Abstract:

In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.

US Patent:

6775788, Aug 10, 2004

Filed:

Sep 5, 2000

Appl. No.:

09/654717

Inventors:

Dominic Paul McCarthy - Los Altos CA
Jack Choquette - Mountain View CA

Assignee:

Raza Microelectronics, Inc. - San Jose CA

International Classification:

G06F 1342

US Classification:

713400, 712 25, 370231

Abstract:

The invention relates to the field of system on a chip, SoC, information processing architecture and particularly to the use of a homogenous, concurrent-communication interconnection architecture that allows a variety of different functions to be connected together and their full synergistic performance realized. The functions are decoupled from each other, allowing performance optimization of each function without regard for the other functions on the chip. The system data flow is coordinated using a overall system schedule allowing data interactions to be orchestrated efficiently.

US Patent:

6782445, Aug 24, 2004

Filed:

May 15, 2001

Appl. No.:

09/763021

Inventors:

Andrea Olgiati - Bristol, GB
Dominic Paul McCarthy - Mountain View CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711100, 711167, 711168, 711118, 711220, 710 35, 710 66, 712 34

Abstract:

In a computer system, a first processor, a second processor for use as a coprocessor to the first processor, a memory, a data buffer for buffering data to be written to or read from the memory in data bursts in accordance with burst instructions, a burst controller for executing the burst instructions, a burst instructions element for providing burst instructions in a sequence for execution by the burst controller, and a synchronization mechanism for synchronizing execution of coprocessor instructions and burst instructions with availability of data on which said coprocessor instructions and burst instructions are to execute. Burst instructions are provided by the first processor to the burst instructions element and data is read from the memory as input data to the second processor and written to the memory as output data from the second processor through the data buffer in accordance with burst instructions executed by the burst controller.

US Patent:

7062767, Jun 13, 2006

Filed:

Sep 5, 2000

Appl. No.:

09/654718

Inventors:

Dominic Paul McCarthy - Los Altos CA, US
Jack Choquette - Mountain View CA, US

Assignee:

Raza Microelectronics, Inc. - Cupertino CA

International Classification:

G06F 9/46

US Classification:

718102, 712225

Abstract:

A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of data transfers in a system is disclosed.

US Patent:

7383424, Jun 3, 2008

Filed:

Jun 15, 2000

Appl. No.:

09/762981

Inventors:

Andrea Olgiati - Newport, GB
Dominic Paul McCarthy - Mountain View CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 15/00

US Classification:

712 34, 712 15, 712228, 711147, 710 5

Abstract:

A computer system comprises a first processor and a second processor for use as a coprocessor to the first processor. The system has a main memory. The system also has a decoupling element such that instructions are passed to the second processor from the first processor through the decoupling element. This has the effects that the second processor consumes instructions derived from the first processor through the decoupling element , and that the second processor receives data from and writes data to the memory. The processing of instructions by the second processor can thus be decoupled from the operation of the first processor This is particularly effective for processing of a computationally intensive task (such as a media computation) on an architecture with a general purpose first processor , using a second processor adapted for the computationally intensive task. This can effectively be combined with use of a buffer memory adapted to exchange data particularly rapidly with the memory in response to memory instructions, together with a further decoupling element to decouple the buffer memory from the first processor.

US Patent:

20230029049, Jan 26, 2023

Filed:

Oct 3, 2022

Appl. No.:

17/959193

Inventors:

- Cupertino CA, US
Tianjia Sun - Santa Clara CA, US
Chang Zhang - San Jose CA, US
Dominic P. McCarthy - Los Altos Hills CA, US
Eric Shyr - San Francisco CA, US
John B. Morrell - Los Gatos CA, US
John P. Ternus - Los Altos Hills CA, US

International Classification:

G09G 5/12
G06F 3/14
G09G 5/14
G06F 3/0346
G06F 1/16
G01D 5/241
H04M 1/72412

Abstract:

A system may include electronic devices that communicate wirelessly. When positioned so that a pair of devices overlap or are adjacent to one another, the devices may operate in a linked mode. During linked operations, devices may communicate wirelessly while input gathering and content displaying operations are shared among the devices. One or both of a pair of devices may have sensors. A capacitive sensor or other sensor may be used to measure the relative position between two devices when the two devices overlap each other. Content displaying operations and other linked mode operations may be performed based on the measured relative position between the two devices and other information.

US Patent:

20170263561, Sep 14, 2017

Filed:

Aug 24, 2016

Appl. No.:

15/246481

Inventors:

- Cupertino CA, US
Peter J. Johnston - San Francisco CA, US
Christine A. Laliberte - Portland OR, US
Dominic P. McCarthy - Los Altos Hills CA, US
Shawn X. Arnold - Santa Cruz CA, US
Souvik Mukherjee - Campbell CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

H01L 23/538
H01L 25/18
H05K 1/16
H01L 23/00
H05K 1/18
H05K 1/11

Abstract:

A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads. The interposer further including isolation resistors embedded within the first array of conductive vias, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor.