Dominik J Schmidt

US Patent:

6452088, Sep 17, 2002

Filed:

Apr 16, 2001

Appl. No.:

09/836111

Inventors:

Dominik J. Schmidt - Palo Alto CA

Assignee:

Airify Communications, Inc. - Stanford CA

International Classification:

H01L 31042

US Classification:

136244, 136291, 136246, 136261, 257431, 257447, 349 28, 349 43

Abstract:

A power-generating active-matrix display includes a first region having a plurality of solar cells arranged in a matrix; and a second region having a plurality of thin film transistors, each of which is associated with a pixel electrode and wherein the solar cells overlie respective pixel electrodes.

US Patent:

6480995, Nov 12, 2002

Filed:

Apr 14, 1997

Appl. No.:

08/840558

Inventors:

Dominik J. Schmidt - San Jose CA
Perry Chun - Milpitas CA
Richard C. Saito - Sunnyvale CA
Y. Eugene Chen - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 11, 716 1, 716 2, 716 8, 716 9

Abstract:

An method of creating a physical layout of an integrated circuit. A schematic file ( ) is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file ( ). The method takes advantage of constraints on the schematic design to provide the layout file ( ) quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

US Patent:

6624495, Sep 23, 2003

Filed:

Jan 30, 1998

Appl. No.:

09/016157

Inventors:

Dominik J. Schmidt - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 2900

US Classification:

257509, 257356, 257368, 257394, 257395

Abstract:

An method and apparatus for high voltage control of isolation region transistors ( ) in an integrated circuit. Isolation region transistors ( ) are formed between active devices by selective implantation of channel stop implants ( ). Isolation region transistors ( ) are those areas with a conductor ( ) over an isolation region ( ) with no channel stop implant ( ). This provides an isolation region transistor ( ) with a lower threshold voltage than the areas with channel stop implant ( ). The voltage threshold of the isolation region transistors are adjustable to a range of voltages by varying the length of channel stop implant ( ). The apparatus may be fabricated using conventional fabrication processes.

US Patent:

6707115, Mar 16, 2004

Filed:

Apr 16, 2001

Appl. No.:

09/836110

Inventors:

Dominik J. Schmidt - Palo Alto CA

Assignee:

AirIP Corporation - Palo Alto CA

International Classification:

H01L 2976

US Classification:

257371, 257548, 257549, 257550, 438223, 438224, 438227, 438228

Abstract:

A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an n-well implanted in the p-well on the drain side; an n+ source region in the p-well outside of the n-well; an n+ drain region within the substrate inside the n-well; and lightly doped regions extending respectively from the source and drain regions toward the gate electrode.

US Patent:

6710424, Mar 23, 2004

Filed:

Sep 21, 2001

Appl. No.:

09/962717

Inventors:

Dominik J. Schmidt - Palo Alto CA

Assignee:

AirIP - Palo Alto CA

International Classification:

H01L 2900

US Classification:

257531, 257601, 4555521

Abstract:

A set of radio frequency (RF) integrated circuits includes a transmit chip having a power amplifier and a receive chip adapted to work with the transmit chip. The receive chip has one or more low noise amplifiers to receive RF signals, and a processor coupled to the low noise amplifiers, the processor transmitting data through the transmit chip and receiving data from the on-chip low noise amplifiers.

US Patent:

6850125, Feb 1, 2005

Filed:

Aug 15, 2001

Appl. No.:

09/930828

Inventors:

Robert D Norman - Blaine WA, US
Dominik J. Schmidt - Palo Alto CA, US

Assignee:

Gallitzin Allegheny LLC - Los Altos CA

International Classification:

H03B 504

US Classification:

331 65, 331 66, 331 68, 331 69

Abstract:

A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.

US Patent:

6853259, Feb 8, 2005

Filed:

Aug 15, 2001

Appl. No.:

09/930822

Inventors:

Robert D Norman - Blaine WA, US
Dominik J. Schmidt - Palo Alto CA, US

Assignee:

Gallitzin Allegheny LLC - Los Altos CA

International Classification:

G01J005/00

US Classification:

331 66, 331176, 374152, 374163, 374170, 374171, 374185, 374208

Abstract:

An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.

US Patent:

6898721, May 24, 2005

Filed:

Jun 22, 2001

Appl. No.:

09/887905

Inventors:

Dominik J. Schmidt - Palo Alto CA, US

Assignee:

Gallitzin Allegheny LLC - Los Altos CA

International Classification:

G06F001/04

US Classification:

713322, 713501, 713600, 455 75, 455205, 455502

Abstract:

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units and the wireless clock input, the clock outputs being generated from a common master clock.