Don G Reid

US Patent:

45119147, Apr 16, 1985

Filed:

Jul 1, 1982

Appl. No.:

6/394239

Inventors:

James J. Remedi - Austin TX
Don G. Reid - Round Rock TX
Lynette Ure - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2702
H01L 2710
H01L 2348
H01L 2715

US Classification:

357 45

Abstract:

A gate array which has power bus routing for increasing current availability to a plurality of transistor cells is provided. The gate array also has separate power busses for input/internal logic and output circuits. The gate array comprises n columns of transistor cells with two power busses extending substantially along each column to power the cells. Input/internal logic power busses and separate output power busses extend around the perimeter of the columns of transistor cells. At least one power strip for increasing current availability to the transistor cells is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.

US Patent:

62295225, May 8, 2001

Filed:

Feb 24, 1999

Appl. No.:

9/256133

Inventors:

Don G. Reid - Round Rock TX

International Classification:

G09G 536

US Classification:

345138

Abstract:

A representation of an image is made from a set of image line signals. The method includes producing a plurality of image component values. Each image component value comprises a value derived from least one selected image line signal included in the set of image line signals. The various image component values are arranged into and ordered sequence and this ordered sequence provides a representation of the image with which the set of image line signals is associated.