Donald J Lee

US Patent:

6828713, Dec 7, 2004

Filed:

Jul 30, 2002

Appl. No.:

10/209624

Inventors:

Paul D. Bradley - Mountain View CA
Donald Lee - San Jose CA
Domingo A. Figueredo - Union City CA

Assignee:

Agilent Technologies, Inc - Palo Alto CA

International Classification:

H01L 4108

US Classification:

310324, 310311, 310364, 29 2535, 333187

Abstract:

A thin-film resonator having a seed layer and a method of making the same are disclosed. The resonator is fabricated having a seed layer to assist in the fabrication of high quality piezoelectric layer for the resoantor. The resonator has the seed layer, a bottom electrode, piezoelectric layer, and a top electrode. The seed layer is often the same material as the piezoelectric layer such as Aluminum Nitride (AlN).

US Patent:

8436516, May 7, 2013

Filed:

Feb 24, 2012

Appl. No.:

13/404095

Inventors:

Richard C. Ruby - Menlo Park CA, US
Wei Pang - Fort Collins CO, US
Qiang Zou - Fort Collins CO, US
Donald Lee - Fort Collins CO, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 41/08

US Classification:

310346, 310320, 310324

Abstract:

An acoustic resonator device includes a composite first electrode on a substrate, a piezoelectric layer on the composite electrode, and a second electrode on the piezoelectric layer. The first electrode includes a buried temperature compensating layer having a positive temperature coefficient. The piezoelectric layer has a negative temperature coefficient, and thus the positive temperature coefficient of the temperature compensating layer offsets at least a portion of the negative temperature coefficient of the piezoelectric layer.

US Patent:

20110266925, Nov 3, 2011

Filed:

Apr 29, 2010

Appl. No.:

12/769791

Inventors:

Richard C. RUBY - Menlo Park CA, US
Wei PANG - Fort Collins CO, US
Qiang ZOU - Fort Collins CO, US
Donald LEE - Fort Collins CO, US

Assignee:

Avago Technologies Wireless IP (Singapore) Pte. Ltd. - Singapore

International Classification:

H01L 41/04

US Classification:

310346

Abstract:

An acoustic resonator device includes a composite first electrode on a substrate, a piezoelectric layer on the composite electrode, and a second electrode on the piezoelectric layer. The first electrode includes a buried temperature compensating layer having a positive temperature coefficient. The piezoelectric layer has a negative temperature coefficient, and thus the positive temperature coefficient of the temperature compensating layer offsets at least a portion of the negative temperature coefficient of the piezoelectric layer.

US Patent:

54736390, Dec 5, 1995

Filed:

Jul 26, 1993

Appl. No.:

8/097688

Inventors:

Donald M. Lee - San Jose CA
Benny W. H. Lai - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H04L 7033

US Classification:

375376

Abstract:

An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i. e. , when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.

US Patent:

55437338, Aug 6, 1996

Filed:

Jun 26, 1995

Appl. No.:

8/494756

Inventors:

Derwin W. Mattos - San Jose CA
Ralph P. Heron - Morgan Hill CA
Donald Lee - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H03K 190175
H03K 19094

US Classification:

326 81

Abstract:

An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal. A comparison and logic control circuit is coupled to the power supply terminal and to the conductor, and is configured to compare a supply voltage level to the input signal and is configured to generate an affirmative logic signal when the input signal is greater than the supply voltage level and to generate a negative logic signal when the input signal is less than the supply voltage level. An N-well control circuit is coupled to the power supply terminal, to the conductor and to the pull-up circuit, where the N-well control circuit is responsive to the logic signal, and is configured to output a control N-well signal to control the PMOS transistor N-well voltage.

US Patent:

50477315, Sep 10, 1991

Filed:

Sep 5, 1990

Appl. No.:

7/577873

Inventors:

Donald M. Lee - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H03G 312

US Classification:

330282

Abstract:

A variable gain wideband bipolar monolithic amplifier has first and second bipolar transistors connected together in a Darlington configuration. A resistive shunt feedback loop connected between the output and the input of the amplifier controls the gain of the amplifier. The feedback loop includes a field effect transistor, formed on the same chip substantially by the same bipolar process as the bipolar transistors, for varying the impedance of the shunt feedback loop thereby varying the gain of the amplifier. The gain of the amplifier is controlled in response to the application of a control voltage to the gate of the FET. Further, the FET is dc biased for inhibiting the FET from drawing dc current.

US Patent:

57480192, May 5, 1998

Filed:

May 15, 1997

Appl. No.:

8/856973

Inventors:

Belle Wong - San Jose CA
Donald Lee - San Jose CA
Derwin Mattos - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H03K 512

US Classification:

327170

Abstract:

A circuit for producing a buffered output includes a power source, a ground, a circuit input, a circuit output, a voltage reference source, a current control pre-driver and an output driver. The circuit input receives an input signal. The circuit output produces an output signal. The voltage reference source generates a reference voltage. The current control pre-driver includes a first current source, a second current source, and control logic. The first current source is connected to the power source and has a first control input. The second current source is connected to the ground and has a second control input. The control logic is connected to the circuit input, to the voltage reference source, to the first control input of the first current source and to the second control input of the second current source. In response to a first voltage value of the input signal on the circuit input, the control logic turns off the second current source and turns on the first current source. The first current source is turned on by connecting the reference voltage to the first control input of the first current source.

US Patent:

20160356842, Dec 8, 2016

Filed:

Jun 2, 2015

Appl. No.:

14/728699

Inventors:

- Tokyo, JP
Donald LEE - San Jose CA, US

International Classification:

G01R 31/28
G01R 1/04
H01R 43/20
H01R 12/70
H01P 5/08

Abstract:

An apparatus for testing DUTs is disclosed. The apparatus comprises a socket operable to enable coupling between a Ball Grid Array (BGA) packaged DUT and a Printed Circuit Board (PCB), wherein the socket comprises a plurality of pogo pin connectors. The apparatus also comprises a pogo pin connector operable to couple a ball on the BGA packaged DUT to a trace on the PCB, wherein the pogo pin connector comprises a first end in contact with the ball on the BGA packaged DUT and a second end in contact with the PCB, wherein the first end is thicker than a shaft of the pogo pin connector, wherein the PCB comprises at least a ground plane and a signal plane comprising signal traces, and wherein the ground plane is nearer to the second end relative to the signal plane.