Donald A Monroe

US Patent:

6653181, Nov 25, 2003

Filed:

Aug 2, 2002

Appl. No.:

10/211674

Inventors:

John Michael Hergenrother - Short Hills NJ
Donald Paul Monroe - Berkeley Heights NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 218238

US Classification:

438206, 438207, 438209, 438212

Abstract:

A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material.

US Patent:

6903411, Jun 7, 2005

Filed:

Aug 25, 2000

Appl. No.:

09/648164

Inventors:

Yih-Feng Chyan - Jersey City NJ, US
John Michael Hergenrother - Short Hills NJ, US
Donald Paul Monroe - Berkeley Heights NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L029/778

US Classification:

257329, 257327, 257328, 257508, 257509

Abstract:

An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer.

US Patent:

61976415, Mar 6, 2001

Filed:

Jun 18, 1999

Appl. No.:

9/335707

Inventors:

John Michael Hergenrother - Short Hills NJ
Donald Paul Monroe - Berkeley Heights NJ
Gary Robert Weber - Whitehouse Station NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 21336

US Classification:

438268

Abstract:

A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate.

US Patent:

60279753, Feb 22, 2000

Filed:

Aug 28, 1998

Appl. No.:

9/143274

Inventors:

John M. Hergenrother - Short Hills NJ
Donald Paul Monroe - Berkeley Heights NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 21336

US Classification:

438268

Abstract:

A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material.

US Patent:

56204965, Apr 15, 1997

Filed:

Dec 4, 1995

Appl. No.:

8/566650

Inventors:

Turan Erdogan - Berkeley Heights NJ
Paul J. Lemaire - Madison NJ
Victor Mizrahi - Bedminster NJ
Donald P. Monroe - Berkeley Heights NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

C03B 3700

US Classification:

65425

Abstract:

The present invention is predicated upon the discovery by applicants of a relationship describing thermal decay of radiation-induced index changes and a mechanism which permits stabilization by accelerated aging. Specifically, the induced index change decays in proportion to 1/(1+At. sup. alpha. ) where A and. alpha. are functions of temperature, and the decay can be accelerated by heat treatment. As a consequence, the extent of decay can be determined for arbitrary time and temperature and, significantly, an appropriate heat treatment can be scheduled for making a device stable within predeterminable limits.

US Patent:

54422051, Aug 15, 1995

Filed:

Aug 9, 1993

Appl. No.:

8/104513

Inventors:

Daniel Brasen - Lake Hiawatha NJ
Eugene A. Fitzgerald - Bridgewater NJ
Martin L. Green - New Providence NJ
Donald P. Monroe - Berkeley Heights NJ
Paul J. Silverman - Millburn NJ
Ya-Hong Xie - Flemington NJ

Assignee:

AT&T Corp. - Murray Hill NJ

International Classification:

H01L 29161
H01L 29205
H01L 29225

US Classification:

257191

Abstract:

A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge. sub. x Si. sub. 1-x epitaxial layer overlain by a ungraded Ge. sub. x. sbsb. 0 Si. sub. 1-x. sbsb. 0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.