Donald James Redwine from Canton, TX, age 83

Name / Title

Company / Classification

Phones & Addresses

Donald Redwine
Managing

REDWINE REMODELING AND RENOVATION, LLC

PO Box 195811, Dallas, TX 75219

Donald C Redwine

VALLEY MOLE CONTROL INC

Circuit And Method For Reducing Sram Standby Power
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US Patent:

6990035, Jan 24, 2006
Filed:

Dec 3, 2003
Appl. No.:

10/727888
Inventors:

Donald J. Redwine - Canton TX, US
Robert R. Doering - Plano TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

G11C 7/00
US Classification:

365227, 365233
Abstract:

A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal () of a memory cell having a first () and a second () data terminal. A data bit is stored in a memory cell (). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.

Sram Cell With Independent Static Noise Margin, Trip Voltage, And Read Current Optimization
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US Patent:

7385840, Jun 10, 2008
Filed:

Jul 28, 2005
Appl. No.:

11/191348
Inventors:

Donald J. Redwine - Canton TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

G11C 11/00
US Classification:

365154, 365156, 36518905
Abstract:

An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.

Sram Static Noise Margin Test Structure Suitable For On Chip Parametric Measurements
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US Patent:

7385864, Jun 10, 2008
Filed:

Sep 12, 2006
Appl. No.:

11/519312
Inventors:

Wah Kit Loh - Richardson TX, US
Donald James Redwine - Canton TX, US
Assignee:

Texas Instruments Incorporated - Dallas TX
International Classification:

G11C 7/00
US Classification:

365201, 365154, 365200, 365206
Abstract:

A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells.