Donald D Shugard

US Patent:

6556152, Apr 29, 2003

Filed:

Jul 20, 2001

Appl. No.:

09/909499

Inventors:

Walter Michael Pitio - Morganville NJ
Donald David Shugard - Middletown NJ

Assignee:

Parama Networks, Inc. - San Jose CA

International Classification:

H03M 900

US Classification:

341101

Abstract:

A deserializer is disclosed that incorporates a detection and feedback mechanism for ensuring that the deserializer samples a serialized stream of bits at advantageous times. Furthermore, a deserializer is disclosed that can operate at a frequency that is below the bit rate of the serialized stream of bits. The illustrative embodiment comprises: a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on the first binary waveform and on the first clock signal; a second bi-stable storage device for receiving the first binary waveform and a second clock signal and for generating a third binary waveform based on the first binary waveform and on the second clock signal; and unanimity logic for generating a fourth binary waveform based on a coincidence function of the second binary waveform and the third binary waveform.

US Patent:

7221687, May 22, 2007

Filed:

May 17, 2002

Appl. No.:

10/150474

Inventors:

Donald David Shugard - Middletown NJ, US

Assignee:

Bay Microsystems, Inc. - San Jose CA

International Classification:

H04J 3/06

US Classification:

370516, 370503, 375358, 375362

Abstract:

A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.

US Patent:

7225219, May 29, 2007

Filed:

Nov 29, 2000

Appl. No.:

09/725732

Inventors:

Peter Joseph Giacomini - South Plainfield NJ, US
Walter Michael Pitio - Morganville NJ, US
Hector Francisco Rodriguez - Middletown NJ, US
Donald David Shugard - Middletown NJ, US

Assignee:

Broadspider Networks, Inc. - Middletown NJ

International Classification:

G06F 15/16

US Classification:

709200, 713154, 713177, 713190

Abstract:

A distributed caching technique for use in computer networks is disclosed. The illustrative embodiment is particularly advantageous in computer networks that comprises a hierarchical topology because it removes some of the computational tasks associated with caching away from the network nodes that act as caches to other network nodes that are less burdened with computational tasks. Furthermore, some embodiments of the present invention use hash tables to facilitate the storage and retrieval of cached resources. The illustrative embodiment of the present invention comprises: hashing at a first processor a first resource identifier to create a hash key, wherein the first resource identifier identifies a first resource; transmitting from the first processor to a second processor the hash key and a request for the first resource; and receiving at the first processor a second resource in response to the transmission of the hash key and the request for the first resource from the first processor to the second processor.

US Patent:

20020103974, Aug 1, 2002

Filed:

Nov 29, 2000

Appl. No.:

09/725737

Inventors:

Peter Giacomini - South Plainfield NJ, US
Walter Pitio - Morganville NJ, US
Hector Rodriguez - Middletown NJ, US
Donald Shugard - Middletown NJ, US

International Classification:

G06F012/00

US Classification:

711/133000, 711/202000

Abstract:

A technique for efficiently populating a cache in a data processing system with resources is disclosed. In particular, a node in accordance with the illustrative embodiment of the present invention defers populating its cache with a resource until at least two requests for the resource have been received. This is advantageous because it prevents the cache from being populated with infrequently requested resources. Furthermore, the illustrative embodiment of the present invention populates a cache with a resource only when: at least i requests for the resource have been received at a given node within an elapsed time interval, t, wherein i is an integer greater than one; and at least one request for the resource has been received from at least n of the m filial nodes of the given node within an elapsed time interval, t, wherein m is an integer greater than one, n is an integer greater than one, and m n. Embodiments of the present invention are particularly advantageous in computer networks that comprise a logical hierarchical topology, but are useful an any computer network, and in individual data processing systems and routers that comprise a cache memory.

US Patent:

20090222624, Sep 3, 2009

Filed:

May 15, 2009

Appl. No.:

12/467000

Inventors:

Peter Joseph Giacomini - South Plainfield NJ, US
Walter Michael Pitio - Morganville NJ, US
Hector Francisco Rodriguez - Middletown NJ, US
Donald David Shugard - Vestal NY, US

Assignee:

BROADSPIDER NETWORKS, INC. - Middletown NJ

International Classification:

G06F 12/08

US Classification:

711125, 711E12016

Abstract:

A technique for efficiently populating a cache in a data processing system with resources is disclosed. In particular, a node in accordance with the illustrative embodiment of the present invention defers populating its cache with a resource until at least two requests for the resource have been received. This is advantageous because it prevents the cache from being populated with infrequently requested resources. Furthermore, the illustrative embodiment of the present invention populates a cache with a resource only when: at least i requests for the resource have been received at a given node within an elapsed time interval, Δt, wherein i is an integer greater than one; and at least one request for the resource has been received from at least n of the m filial nodes of the given node within an elapsed time interval, Δt, wherein m is an integer greater than one, n is an integer greater than one, and m≧n. Embodiments of the present invention are particularly advantageous in computer networks that comprise a logical hierarchical topology, but are useful an any computer network, and in individual data processing systems and routers that comprise a cache memory.

US Patent:

53176588, May 31, 1994

Filed:

Apr 6, 1992

Appl. No.:

7/864293

Inventors:

Glenn D. Bergland - Berkeley Heights NJ
John V. Camlet - Cranford NJ
Saul J. Einbinder - Holmdel NJ
Walter M. Pitio - Old Bridge NJ
Robert C. Pritchard - Middletown NJ
George J. Shevchuk - Old Bridge NJ
Donald D. Shugard - Middletown NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G02B 626

US Classification:

385 16

Abstract:

An apparatus and method are disclosed for implementing a polarization-independent optical switch wherein switchable communication signals are retained in the optical mode while being switched between optical links in an optical communication network. The polarization-independent optical switch comprises polarization-dependent components which are advantageously arranged to switch arbitrary polarized light waves. The polarization-independent optical switch is achieved by splitting incoming arbitrary polarized light waves into two paths, a light wave with a TE radiation component and a light wave with a TM radiation component. The light wave with the TE radiation component is converted to a light wave with a TM radiation component. Both light waves having the TM radiation component are then switched in a polarization-dependent photonic switch device. The arbitrary light waves are recovered from the optical switch by converting one of the switched light waves having the TM radiation component to a light wave having the TE radiation component.

US Patent:

53608828, Nov 1, 1994

Filed:

Feb 4, 1994

Appl. No.:

8/192079

Inventors:

James A. Dougherty - Pequannock NJ
Donald J. Shugard - Berkeley Heights NJ
Lowell R. Anderson - Morristown NJ

Assignee:

ISP Investments Inc. - Wilmington DE

International Classification:

C08F 2240

US Classification:

526262

Abstract:

Eutectic compositions of vinyl caprolactam (VCL) and divinyl imidazolidone (DVI) which are liquids at room temperature are described. These compositions are useful as reactive diluents in curable coating formulations.

US Patent:

58349804, Nov 10, 1998

Filed:

Jun 30, 1994

Appl. No.:

8/268752

Inventors:

Walter M. Pitio - Old Bridge NJ
Donald D. Shugard - Middletown NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H03L 707

US Classification:

331 2

Abstract:

A method and apparatus for recovering the time base of signals which change at periodic intervals is disclosed. The apparatus comprises gated voltage controlled oscillators (GVCO) that are alternated or exchanged, to reduce phase and frequency deviations in the recovered time base signal, such as the deviations induced by inherent GVCO differences. Each GVCO is stabilized by a respective phase locked loop. The respective GVCOs are gated only in response to a chosen polarity transition in the input signal, to make the circuit more tolerant of waveform distortions. More than two GVCOs may be used to provide improved frequency drift resistance. The circuit uses resynchronization control signals, such as the time slot signal in synchronous switching systems, to indicate resynchronization or reassignment of the GVCOs in gaps in the data transmission. Automatic reassignment is insured when there are periods of non-transitioning data that last longer than the stability of the GVCOs to prevent frequency drift in the recovered clock.