Donald S Walters

US Patent:

7765425, Jul 27, 2010

Filed:

Mar 21, 2006

Appl. No.:

11/385329

Inventors:

Shawn Searles - Austin TX, US
Donald Walters - Austin TX, US
Ravinder Rachala - Austin TX, US
Scott C. Johnson - Round Rock TX, US

Assignee:

GlobalFoundries, Inc. - Grand Cayman

International Classification:

G06F 1/04

US Classification:

713503, 713401

Abstract:

A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.

US Patent:

7770049, Aug 3, 2010

Filed:

Mar 21, 2006

Appl. No.:

11/385328

Inventors:

Shawn Searles - Austin TX, US
Scott C. Johnson - Round Rock TX, US
Donald Walters - Austin TX, US
Ravinder Rachala - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/04

US Classification:

713503, 713401

Abstract:

Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.

US Patent:

48003000, Jan 24, 1989

Filed:

Nov 2, 1987

Appl. No.:

7/115279

Inventors:

Donald M. Walters - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1140

US Classification:

307279

Abstract:

A CMOS latch circuit is provided which eliminates the lowering of a high voltage level from a precharge/discharge data bus line caused by charge-sharing effect. The CMOS latch circuit is formed of a P-channel precharge transistor (P1), a P-channel drive transistor (P2), an N-channel drive transistor (N1), an N-channel enable transistor (N2), and a transimission gate (TG) for loading a complementary data input signal to a storage node (A) in response to true and complementary load signals. The latch circuit further includes output transistor devices formed of a pair of P-channel output transistors (P3, P4) and a pair of N-channel output transistors (N3, N4) which are all connected in series, and are responsive to true and complementary load signals and to true and complementary data output signals for maintaining the latch circuit in one of two states.

US Patent:

48048712, Feb 14, 1989

Filed:

Jul 28, 1987

Appl. No.:

7/078746

Inventors:

Donald M. Walters - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 1716

US Classification:

807530

Abstract:

A sense amplifier includes a pair of decoupling transistors (P4, P5) for isolating the sense nodes (X, Y) from the bit lines (B, B) during the assertion of a sense signal, thereby eliminating the occurrence of current spikes and increasing its gain.

US Patent:

48067946, Feb 21, 1989

Filed:

Jul 22, 1987

Appl. No.:

7/076566

Inventors:

Donald M. Walters - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19094
H03K 1716
H03K 1920

US Classification:

307451

Abstract:

A CMOS output buffer includes a transient pull-up circuit, a transient pull-down circuit and a keeper circuit. The pull-up circuit is responsive to a high drive enable pulse signal for generating a transition from a low logic level to a high logic level at an output node. The pull-down circuit is responsive to a low drive enable pulse signal for generating a transition from the high logic level to the low logic level at the output node. The keeper circuit is responsive to the high and low drive enable pulse signals so as to maintain the output node at the high logic level after the output node has made the low-to-high transition and to maintain the output node at the low logic level after the output node has made the high-to-low transition. The CMOS output buffer has a high speed of operation and has a high immunity to noise.

US Patent:

48412791, Jun 20, 1989

Filed:

Oct 30, 1987

Appl. No.:

7/115130

Inventors:

Donald M. Walters - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 702

US Classification:

3401462

Abstract:

A data compare circuit includes an inverter (I1), a first group (20) of series-connected transistors, a second group (20) of series-connected transistors, and a switching device (24). The switching device (24) causes a common equal line (18) to be discharged from a precharged high voltage level to a low logic level when an equality does not exist.

US Patent:

50417380, Aug 20, 1991

Filed:

Dec 4, 1989

Appl. No.:

7/445245

Inventors:

Donald M. Walters - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 513
H03K 19094
H01H 3736

US Classification:

307269

Abstract:

A CMOS clock generator for generating internal CMOS phase clock signals having an adjustable overlap voltage includes a first circuit (18) having a first input responsive to an input clock signal for generating a first phase clock signal (01) on its output and a second circuit (22) having a first input responsive to the input clock signal for generating a second clock signal (02) on its output. The overlap voltage between the phase clock signals are adjustable either up or down to speed up or slow down a semiconductor chip after fabrication. This is achieved by the utilization of a laser to break or open up fuses connected to electrodes of transistor devices.

US Patent:

57137145, Feb 3, 1998

Filed:

Nov 8, 1995

Appl. No.:

8/555211

Inventors:

Donald E. Walters - Channelview TX

Assignee:

Jerr-Dan Corporation - Greencastle PA

International Classification:

B60P 312

US Classification:

414563

Abstract:

The present invention is directed a tilt cylinder assembly for an underlift assembly for attachment to a recovery vehicle. The present invention provides for rotation of the horizontal member about a first and second pivot point. The first pivot point is where the lifters attach to the horizontal member. The second pivot point is formed by attaching a forward end of the horizontal member to a tilt cylinder assembly including at least one lifter. The tilt cylinder assembly lifter provides for movement of the second pivot point. By providing two pivot points, the operator of the underlift assembly is allowed more flexibility in positioning.