Dong Wook Kim

Address:

281 Del Valle Ct, Pleasanton, CA 94566

Phone:

(510)7935577

VIN:

5TDKK3DC2BS160485

Make:

TOYOTA

Model:

SIENNA

Year:

2011

Address:

25257 Nesting Sq, Chantilly, VA 20152

VIN:

2HNYD2H6XBH505483

Make:

ACURA

Model:

MDX

Year:

2011

US Patent:

6787409, Sep 7, 2004

Filed:

Nov 26, 2002

Appl. No.:

10/305464

Inventors:

Hua Ji - San Jose CA
Dong Jun Kim - San Jose CA
Jin-Ho Kim - San Jose CA
Chuck Jang - Fremont CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 218238

US Classification:

438221, 438296, 438424, 438426, 438431, 438435

Abstract:

A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

US Patent:

6864148, Mar 8, 2005

Filed:

Sep 5, 2003

Appl. No.:

10/655705

Inventors:

Chia-Shun Hsiao - Cupertino CA, US
Dong Jun Kim - San Jose CA, US

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L021/76
H01L021/3205
H01L021/31

US Classification:

438400, 438424, 438595, 438780

Abstract:

A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

US Patent:

6924542, Aug 2, 2005

Filed:

Jul 29, 2004

Appl. No.:

10/901948

Inventors:

Hua Ji - San Jose CA, US
Dong Jun Kim - San Jose CA, US
Jin-Ho Kim - San Jose CA, US
Chuck Jang - Fremont CA, US

Assignee:

ProMos Technologies, Inc. - Hsin Chu

International Classification:

H01L029/00
H01L021/8238

US Classification:

257501, 257506, 257510, 257513, 438221, 438296, 438426, 438435

Abstract:

A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.

US Patent:

7196381, Mar 27, 2007

Filed:

Jan 31, 2005

Appl. No.:

11/048668

Inventors:

Chia-Shun Hsiao - Cupertino CA, US
Dong Jun Kim - San Jose CA, US

Assignee:

Promos Technologies Pte. Ltd. - Districentre

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257374, 257397, 257510

Abstract:

A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

US Patent:

7358149, Apr 15, 2008

Filed:

Jul 29, 2005

Appl. No.:

11/193150

Inventors:

Daniel Wang - San Jose CA, US
Chunchieh Huang - Fremont CA, US
Dong Jun Kim - San Jose CA, US

Assignee:

ProMOS Technologies, Inc. - Hsin-Chu

International Classification:

H01L 21/425

US Classification:

438433, 438525, 257E21551

Abstract:

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e. g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

US Patent:

7387942, Jun 17, 2008

Filed:

Dec 9, 2003

Appl. No.:

10/732616

Inventors:

Daniel Wang - San Jose CA, US
Chunchieh Huang - Fremont CA, US
Dong Jun Kim - San Jose CA, US

Assignee:

ProMOS Technologies Inc. - Hsin-Chu

International Classification:

H01L 21/425
H01L 21/762

US Classification:

438433, 438524, 438525, 257E21345

Abstract:

Substrate isolation trench () are formed in a semiconductor substrate (). Dopant (e. g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transistor gate dielectric () faces the ion stream, but damage to the gate dielectric is annealed in subsequent thermal steps. In some embodiments, the dopant implantation is an angled implant. The implant is performed from the opposite sides of the wafer, and thus from the opposite sides of each active area. Each active area includes a region implanted from one side and a region implanted from the opposite side. The two regions overlap to facilitate threshold voltage adjustment.

US Patent:

8258013, Sep 4, 2012

Filed:

Feb 12, 2010

Appl. No.:

12/705441

Inventors:

Kumar Nagarajan - San Jose CA, US
S. Gabriel R. Dosdos - San Jose CA, US
Dong W. Kim - San Jose CA, US
Kong W. Lee - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/10
H01L 21/00

US Classification:

438115, 257678, 257704, 438106

Abstract:

An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.

US Patent:

8362609, Jan 29, 2013

Filed:

Oct 27, 2009

Appl. No.:

12/607019

Inventors:

S. Gabriel R. Dosdos - San Jose CA, US
Dong Wook Kim - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/04

US Classification:

257730, 257690, 257704, 257E21499, 438121

Abstract:

An integrated circuit package is described. The integrated circuit package comprises a substrate having a plurality of sides, where each pair of adjacent sides forms a corner; a die coupled to a first surface of the substrate; a lid having a first portion positioned over the die and a plurality of foot portions, each foot portion of the plurality of foot portions being coupled to the first surface of the substrate at a corresponding corner of the substrate, where a side of the integrated circuit package above the substrate and between two associated foot portions has an opening; and a plurality of contact elements coupled to a second surface of the substrate. A method of forming an integrated circuit package is also shown.