Donovan Scott Popps

US Patent:

59236159, Jul 13, 1999

Filed:

Apr 17, 1998

Appl. No.:

9/061953

Inventors:

Derrick Andrew Leach - Austin TX
Donovan Scott Popps - Austin TX
Frank Arlen Miller - Austin TX

Assignee:

Motorlola - Schaumburg IL

International Classification:

G11C 700

US Classification:

3652385

Abstract:

A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which latches a burst address during a first cycle of a periodic clock signal. The burst address is driven to an input of an asynchronous memory core (40), but output data from the asynchronous memory core (40) is not latched until a third cycle of the periodic clock signal which occurs after a second cycle of the periodic clock signal which is immediately subsequent to the first cycle. The memory (20) outputs successive data elements of the burst during consecutive cycles of the periodic clock signal to complete the burst cycle.

US Patent:

20200257352, Aug 13, 2020

Filed:

May 1, 2020

Appl. No.:

16/864155

Inventors:

- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US

International Classification:

G06F 1/3234
G06F 1/3296
G11C 5/14
G06F 1/3237
G06F 1/3203
G06F 1/26
G06F 1/3287

Abstract:

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

US Patent:

20200159279, May 21, 2020

Filed:

Jan 27, 2020

Appl. No.:

16/773160

Inventors:

- Austin TX, US
Scott Hanson - Austin TX, US
Donovan Popps - Austin TX, US

International Classification:

G06F 1/06
H02M 3/158
G06F 1/3296
G05F 1/575
H03L 7/00
H03M 1/12
H03K 17/687
G05F 1/56
G01R 19/00
G06F 13/10
G06F 11/34
G06F 11/30
G06F 1/12
G06F 1/3287
G06F 1/3237
H03L 7/181
H03L 7/06
H03L 7/18

Abstract:

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

US Patent:

20190079573, Mar 14, 2019

Filed:

Mar 22, 2018

Appl. No.:

15/933153

Inventors:

- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US

International Classification:

G06F 1/32

Abstract:

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

US Patent:

20190079574, Mar 14, 2019

Filed:

Jun 11, 2018

Appl. No.:

16/005315

Inventors:

- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US

International Classification:

G06F 1/32

Abstract:

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

US Patent:

20190079575, Mar 14, 2019

Filed:

Jun 20, 2018

Appl. No.:

16/013767

Inventors:

- Austin TX, US
Daniel Martin Cermak - Austin TX, US
Eric Jonathan Deal - Austin TX, US
Stephen James Sheafor - Boulder CO, US
Donovan Scott Popps - Austin TX, US
Mark A. Baur - Austin TX, US

International Classification:

G06F 1/32

Abstract:

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

US Patent:

20190050019, Feb 14, 2019

Filed:

Aug 10, 2017

Appl. No.:

15/674242

Inventors:

- Austin TX, US
Donovan Scott Popps - Austin TX, US

International Classification:

G06F 1/08
G06F 13/42
G06F 1/12

Abstract:

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

US Patent:

20180150099, May 31, 2018

Filed:

Dec 14, 2017

Appl. No.:

15/841673

Inventors:

- Austin TX, US
Scott Hanson - Austin TX, US
Donovan Popps - Austin TX, US

Assignee:

Ambiq Micro, Inc. - Austin TX

International Classification:

G06F 1/06
G01R 19/00
G05F 1/56
G06F 1/12
G06F 1/32
G06F 11/30
G06F 11/34
G06F 13/10
H03K 17/687
H03L 7/00
H03M 1/12

Abstract:

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.