Douglas B Boyle

US Patent:

6367051, Apr 2, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/096810

Inventors:

Lawrence Pileggi - Pittsburgh PA
Sharad Malik - Princeton NJ
Emre Tuncer - Palo Alto CA
Abhijeet Chakraborty - Sunnyvale CA
Satyamurthy Pullela - Cupertino CA
Altan Odabasioglu - Sunnyvale CA
Douglas B. Boyle - Palo Alto CA

Assignee:

Monterey Design Systems, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 2, 716 7

Abstract:

A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

US Patent:

6385760, May 7, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/096804

Inventors:

Lawrence Pileggi - Pittsburgh PA
Majid Sarrafzadeh - Wilmette IL
Gary K. Yeap - San Jose CA
Feroze Peshotan Taraporevala - San Jose CA
Tong Gao - Fremont CA
Douglas B. Boyle - Palo Alto CA

Assignee:

Monterey Design Systems, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 8, 716 2, 716 7

Abstract:

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

US Patent:

6442743, Aug 27, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/097107

Inventors:

Majid Sarrafzadeh - Wilamette IL
Lawrence Pileggi - Pittsburgh PA
Sharad Malik - Princeton NJ
Feroze Peshotan Taraporevala - San Jose CA
Abhijeet Chakraborty - Sunnyvale CA
Gary K. Yeap - San Jose CA
Salil R. Raje - Santa Clara CA
Lilly Shieh - Union City CA
Douglas B. Boyle - Palo Alto CA
Dennis Yamamoto - Los Altos CA

Assignee:

Monterey Design Systems - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 10, 716 9

Abstract:

The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.

US Patent:

6449756, Sep 10, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/094542

Inventors:

Sharad Malik - Princeton NJ
Lawrence Pileggi - Pittsburgh PA
Eric McCaughrin - Oakland CA
Abhijeet Chakraborty - Sunnyvale CA
Douglas B. Boyle - Palo Alto CA

Assignee:

Monterey Design Systems - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 6, 716 2, 716 4

Abstract:

A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

US Patent:

6493658, Dec 10, 2002

Filed:

Apr 19, 1994

Appl. No.:

08/229616

Inventors:

James S. Koford - San Jose CA
Michael D. Rostoker - Boulder Creek CA
Edwin R. Jones - Sunnyvale CA
Douglas B. Boyle - Palo Alto CA
Ranko Scepanovic - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

703 1, 716 9, 716 10

Abstract:

A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.

US Patent:

6557145, Apr 29, 2003

Filed:

Mar 6, 2001

Appl. No.:

09/801010

Inventors:

Douglas B. Boyle - Palo Alto CA
James S. Koford - San Jose CA

Assignee:

Monterey Design Systems, Inc. - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 2, 716 7, 716 8

Abstract:

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

US Patent:

6961916, Nov 1, 2005

Filed:

May 1, 2002

Appl. No.:

10/136161

Inventors:

Majid Sarrafzadeh - Wilamette IL, US
Lawrence Pileggi - Pittsburgh PA, US
Sharad Malik - Princeton NJ, US
Feroze Peshotan Taraporevala - San Jose CA, US
Abhijeet Chakraborty - Sunnyvale CA, US
Gary K. Yeap - San Jose CA, US
Salil R. Raje - Santa Clara CA, US
Lilly Shieh - Union City CA, US
Douglas B. Boyle - Palo Alto CA, US
Dennis Yamamoto - Los Altos CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F017/50

US Classification:

716 10, 716 2, 716 7, 716 9

Abstract:

The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM.

US Patent:

8035139, Oct 11, 2011

Filed:

Aug 20, 2008

Appl. No.:

12/194651

Inventors:

Douglas B. Boyle - Saratoga CA, US

Assignee:

SuVolta, Inc. - Los Gatos CA

International Classification:

H01L 29/66

US Classification:

257256, 257272, 257392, 257E21631

Abstract:

A dynamic random access memory (DRAM) device can include a plurality of memory cells. Each memory cell can include a charge storing structure and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device can further include a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. A method can fabricate such DRAM devices.