Douglas J Boyle

US Patent:

6449756, Sep 10, 2002

Filed:

Jun 12, 1998

Appl. No.:

09/094542

Inventors:

Sharad Malik - Princeton NJ
Lawrence Pileggi - Pittsburgh PA
Eric McCaughrin - Oakland CA
Abhijeet Chakraborty - Sunnyvale CA
Douglas B. Boyle - Palo Alto CA

Assignee:

Monterey Design Systems - Sunnyvale CA

International Classification:

G06F 1750

US Classification:

716 6, 716 2, 716 4

Abstract:

A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

US Patent:

6192508, Feb 20, 2001

Filed:

Jun 12, 1998

Appl. No.:

9/097076

Inventors:

Sharad Malik - Princeton NJ
Lawrence Pileggi - Pittsburgh PA
Abhijeet Chakraborty - Sunnyvale CA
Gary K. Yeap - San Jose CA
Douglas B. Boyle - Palo Alto CA

Assignee:

Monterey Design Systems - Sunneyvale CA

International Classification:

G06F 1750

US Classification:

716 9

Abstract:

This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.