Douglas Alexander Chapman

US Patent:

57899584, Aug 4, 1998

Filed:

Jan 13, 1997

Appl. No.:

8/782608

Inventors:

Douglas J. Chapman - Lake Oswego OR
Jeffrey D. Currin - Pleasanton CA
Philip Theodore Kuglin - Tualatin OR

Assignee:

Credence Systems Corporation - Fremont CA

International Classification:

H03K 513

US Classification:

327261

Abstract:

A timing signal generator adjustably times successive pulses of an output timing signal. The generator receives input data before each output pulse and controls the timing of that output pulse in accordance with the input data. The generator includes a circuit providing a set of 2N phase signals frequency locked to a reference clock signal but evenly distributed in phase. First and second selectors each sample the data once during each cycle of the clock signal. The sampled data tells the first selector whether it is to produce a first output signal during the next clock signal cycle and, if so, which of the first N phase signals the first selector is to select for controlling timing of edges of the first output signal. The sampled data also tells the second selector whether it is to produce a second output signal during a next clock signal cycle and, if so, which of the second N phase signals the second selector is to select for controlling the second output signal. The first and second output signals are logically ORed to produce the timing signal.

US Patent:

56844212, Nov 4, 1997

Filed:

Oct 13, 1995

Appl. No.:

8/542518

Inventors:

Douglas J. Chapman - Lake Oswego OR
Jeffrey D. Currin - Pleasanton CA

Assignee:

Credence Systems Corporation - Fremont CA

International Classification:

H03K 513
H03K 526

US Classification:

327261

Abstract:

A timing vernier produces a set of timing signals of similar frequency and evenly distributed in phase by passing an input reference clock signal through a succession of delay stages, each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller through separate adjustable first and second delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted to compensate for controller phase lock error.