Douglas D Hunt

US Patent:

63082616, Oct 23, 2001

Filed:

Jan 30, 1998

Appl. No.:

9/016692

Inventors:

Dale C. Morris - Menlo Park CA
Douglas B. Hunt - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 938

US Classification:

712219

Abstract:

A computer system includes a data structure that maintains availability status for registers of a processor of the computer system, wherein the availability status indicates whether an instruction attempting to read a particular register will stall. The computer system also includes instruction decode and execution circuitry that is capable of decoding and executing one or more instructions that alter a path of program execution based on the availability status of one or more of the registers. In one embodiment, a latency probe instruction retrieves the availability status of a register from the data structure and stores the availability status in a register. Thereafter, a conditional branch instruction determines the path of program execution based on the availability status stored in the register. In another embodiment, a conditional branch instruction queries the data structure directly to determine the availability status of a register, and determines the execution path based on the availability status. By exposing the latency of memory operations to programs, a compiler can schedule alternate threads of execution based on varying latencies.

US Patent:

50560913, Oct 8, 1991

Filed:

Mar 15, 1990

Appl. No.:

7/494005

Inventors:

Douglas B. Hunt - Mountain View CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1100

US Classification:

371 14

Abstract:

A quick freeze method and a clean freeze method allow for the halting of operation of all computing sections within a computing system upon detection of an error. In the quick freeze method, a first computing section detecting an error immediately halts operation. The first computing section notifies all adjacent computing sections of the detection of the error. Each computing section in the computing system, upon receiving notification of the detection of the error, immediately halts operation and notifies all adjacent computing sections of the detection of the error. In the clean freeze method, when a first computing section detects an error, all computing sections are notified of the detection of the error. When all computing sections of the computing system have been notified, all the computing sections within the computing system halt operation simultaneously. In order to allow for versatility, a computing system may be designed to allow the selection, at configuration, of either the clean freeze or the quick freeze method of halting operation of the computing system.

US Patent:

51558327, Oct 13, 1992

Filed:

Jul 5, 1989

Appl. No.:

7/376265

Inventors:

Douglas B. Hunt - Mountain View CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor. A second cache memory is connected to the processor and to the system memory. The second cache memory contains a subset of data in the system memory. The first cache memory contains a subset of data in the second cache memory. Data integrity in the system memory is maintained using the second cache memory only. During the execution of a first instruction data required for execution of the first instruction might not be available in the first cache memory. The data required for execution of the first instruction is obtained from the second cache memory and written into the first cache memory. If, however, there is an attempt to access from the first cache memory data required for a second instruction, and this attempt to access the first cache memory occurs simultaneously to the time when the data required for execution of the first instruction is being written from the school cache memory to the first cache memory, then a cache miss is forced and the second cache memory is accessed for the data required for execution of the second instruction.