Douglas Martin Mattingly

US Patent:

7301317, Nov 27, 2007

Filed:

Dec 18, 2003

Appl. No.:

10/739511

Inventors:

Douglas M. Mattingly - Garner NC, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

G05F 1/40

US Classification:

323282

Abstract:

A regulator with output current sharing including an output node and multiple converters. Each converter includes a PWM controller and switch circuit, an inductor, and an RC circuit. Each PWM controller and switch circuit receives a corresponding rail voltage and has a phase node and a regulation feedback input. Each inductor has a first end coupled to the output node and a second end coupled to a corresponding phase node. The RC circuit is coupled across the inductor and has an intermediate phase sense node coupled to a corresponding regulation feedback input. Each RC circuit may include an RC filter coupled across an inductor with an intermediate node and a feedback circuit coupled between the intermediate node and a regulation feedback input. The RC circuits may be configured to program a relative power distribution between the rail voltages to the shared output.

US Patent:

7368959, May 6, 2008

Filed:

Jun 29, 2006

Appl. No.:

11/427654

Inventors:

Jun Xu - McKinney TX, US
Zbigniew Lata - Plano TX, US
Douglas M. Mattingly - Garner NC, US
Bogdan M. Duduman - Raleigh NC, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H03L 7/00

US Classification:

327141, 327540

Abstract:

An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

US Patent:

8305070, Nov 6, 2012

Filed:

Aug 20, 2010

Appl. No.:

12/860317

Inventors:

Salomon Vulih - Hillsborough NJ, US
Timothy Maher - Branchburg NJ, US
Douglas M Mattingly - Bahama NC, US

Assignee:

Intersil Americas Inc. - Milpitas CA

International Classification:

H02J 1/00
H02J 3/12

US Classification:

323318, 323320, 323322, 323325, 323282, 323283

Abstract:

A controller and methodology for a power supply are disclosed. The controller includes output channels for providing a pulse width modulation (PWM) voltage signal for driving a load, for example, a microprocessor. Each channel provides a portion of the PWM signal. The controller receives user input information and uses that information to automatically determine window sizes. A window size defines the maximum output current level for a given window. The controller uses feedback signals to determine the current being drawn by the load, and selects the number of windows and channels that are needed to adequately provide that current. The controller selectively activates and deactivates the output channels accordingly. In response a change in the user input information the controller automatically adjusts the window sizes.

US Patent:

20170110963, Apr 20, 2017

Filed:

Feb 1, 2016

Appl. No.:

15/012786

Inventors:

- Milpitas CA, US
Douglas M. Mattingly - Bahama NC, US

International Classification:

H02M 3/158
G06F 1/28
G01R 31/40

Abstract:

An electronic system, voltage regulator, controller and fault reporting method and circuit for a voltage regulator or other type of DC-DC converter are disclosed. For example, a fault reporting circuit is disclosed. The fault reporting circuit includes a first transistor device configured to generate a first signal indicating an occurrence of a fault in an associated circuit, a second transistor device coupled to the first transistor device, the second transistor device configured to generate at least one data signal indicating an identity of the fault in the associated circuit, and an output coupled to the first transistor device and the second transistor device, wherein the output is configured to receive the first signal and the at least one data signal. In some implementations, the fault reporting circuit is in a controller for a voltage regulator circuit formed on one or more semiconductor ICs, wafers, chips or dies.