Douglas James Tweet

US Patent:

6506637, Jan 14, 2003

Filed:

Apr 12, 2001

Appl. No.:

09/834488

Inventors:

Jer-shen Maa - Vancouver WA
Douglas James Tweet - Camas WA
Sheng Teng Hsu - Camas WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 2100

US Classification:

438152, 438149, 438259, 438294, 438299

Abstract:

A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800Â C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i. e. , the resistance remains low when annealing temperatures extend up to and beyond 800Â C.

US Patent:

6534871, Mar 18, 2003

Filed:

May 14, 2001

Appl. No.:

09/855391

Inventors:

Jer-shen Maa - Vancouver WA
Douglas J. Tweet - Camas WA
Yoshi Ono - Camas WA
Fengyan Zhang - Vancouver WA
Sheng Teng Hsu - Camas WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 2348

US Classification:

257769, 257754, 257757, 257768

Abstract:

An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i. e. , without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

US Patent:

6555874, Apr 29, 2003

Filed:

Aug 28, 2000

Appl. No.:

09/649380

Inventors:

Sheng Teng Hsu - Camas WA
Douglas James Tweet - Camas WA
Bruce Dale Ulrich - Beaverton OR
Hong Ying - Vancouver WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 310392

US Classification:

257347, 257349, 257350, 257351

Abstract:

A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.

US Patent:

6562703, May 13, 2003

Filed:

Mar 13, 2002

Appl. No.:

10/099374

Inventors:

Jer-Shen Maa - Vancouver WA
Douglas J. Tweet - Camas WA
Sheng Teng Hsu - Camas WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 21265

US Classification:

438518, 438522, 438933, 257 55

Abstract:

A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si Ge ) overlying the Si buffer layer having a thickness of 1000 to 5000 ; implanting the Si Ge layer with ionized molecular hydrogen (H ) a projected range of approximately 100 to 300 into the underlying Si buffer layer; optionally, implanting the Si Ge layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si Ge layer to a relaxed Si Ge layer. Optionally, after annealing, an additional layer of single-crystal Si Ge having a thickness of greater than 1000 can be deposited overlying the relaxed layer of Si Ge.

US Patent:

6583000, Jun 24, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072183

Inventors:

Sheng Teng Hsu - Camas WA
Jer-shen Maa - Vancouver WA
Douglas James Tweet - Camas WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 218238

US Classification:

438222, 438221, 438430, 438528, 438692

Abstract:

A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700Â C. to 900Â C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.

US Patent:

6620664, Sep 16, 2003

Filed:

Feb 7, 2002

Appl. No.:

10/072248

Inventors:

Yanjun Ma - Seattle WA
Douglas James Tweet - Camas WA
David Russell Evans - Beaverton OR

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 21338

US Classification:

438183, 438162

Abstract:

An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

US Patent:

6627510, Sep 30, 2003

Filed:

Mar 29, 2002

Appl. No.:

10/112014

Inventors:

David R. Evans - Beaverton OR
Sheng Teng Hsu - Camas WA
Bruce D. Ulrich - Beaverton OR
Douglas J. Tweet - Camas WA
Lisa H. Stecker - Vancouver WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 21762

US Classification:

438401, 438975

Abstract:

A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer.

US Patent:

6627919, Sep 30, 2003

Filed:

Dec 12, 2002

Appl. No.:

10/319312

Inventors:

Jer-shen Maa - Vancouver WA
Douglas James Tweet - Camas WA
Sheng Teng Hsu - Camas WA

Assignee:

Sharp Laboratories of America, Inc. - Camas WA

International Classification:

H01L 2976

US Classification:

257 67, 257 51, 257 52, 257 64, 257 65, 257 66, 257 68, 257 69, 257347

Abstract:

A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800Â C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i. e. , the resistance remains low when annealing temperatures extend up to and beyond 800Â C.