Duane R Aadsen

US Patent:

7191280, Mar 13, 2007

Filed:

Dec 23, 2003

Appl. No.:

10/744798

Inventors:

Duane Rodney Aadsen - Bath PA, US
Dennis E. Dudeck - Hazleton PA, US
Donald A. Evans - Lancaster OH, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 12/00

US Classification:

711108, 365 49

Abstract:

Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card inputs of the binary CAM. The match search inputs of the binary CAM are tied to a power supply voltage.

US Patent:

7254763, Aug 7, 2007

Filed:

Sep 1, 2004

Appl. No.:

10/931709

Inventors:

Duane Rodney Aadsen - Bath PA, US
Ilyoung I. Kim - Franklin Park NJ, US
Ross Alan Kohler - Allentown PA, US
Richard Joseph McPartland - Nazareth PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G01R 31/28

US Classification:

714733

Abstract:

A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations. The test control circuit provides a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.

US Patent:

7363424, Apr 22, 2008

Filed:

Jan 4, 2007

Appl. No.:

11/619889

Inventors:

Duane Rodney Aadsen - Bath PA, US
Dennis E. Dudeck - Hazleton PA, US
Donald A. Evans - Lancaster OH, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 12/00

US Classification:

711108

Abstract:

Content addressable memories are disclosed that provide at least three states and are based on existing binary CAM devices. A higher order CAM having at least three states comprises a binary CAM having two binary bits; and a logic circuit to configure the two binary bits as a single CAM bit having said at least three states. The three states include a don't care state, a logic 0 state and a logic 1 state. The logic circuit may be embodied as two OR gates. The first match search (MS) input and a first wild card (WC) input of the higher order CAM are applied to inputs of the two OR gates and the outputs of the two OR gates are applied to the wild card (WC) inputs of the binary CAM. The match search (MS) inputs of the binary CAM are tied to a power supply voltage.