Dung H Tran

US Patent:

6728140, Apr 27, 2004

Filed:

Dec 5, 2001

Appl. No.:

10/011157

Inventors:

Kyung Joon Han - Palo Alto CA
Joo Weon Park - Pleasanton CA
Dung Tran - San Jose CA
Steve K. Hsia - San Jose CA
Jong Seuk Lee - Palo Alto CA
Dae Hyun Kim - Fremont CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518524, 36518526, 3651853, 36518529

Abstract:

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

US Patent:

6731544, May 4, 2004

Filed:

Nov 8, 2001

Appl. No.:

10/039518

Inventors:

Kyung Joon Han - Palo Alto CA
Dung Tran - San Jose CA
Steven W. Longcor - Mountain View CA
Steve K. Hsia - San Jose CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518528, 36518717, 36518518

Abstract:

A memory array contains memory cells designed to be erased using Fowler-Nordheim (âFNâ) tunneling through the channel area, and programmed using either channel hot electron injection (âCHEâ) or channel-initiated secondary electron injection (âCISEIâ). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

US Patent:

6747899, Jun 8, 2004

Filed:

Nov 8, 2001

Appl. No.:

10/035414

Inventors:

Steve K. Hsia - San Jose CA
Kyung Joon Han - Palo Alto CA
Dung Tran - San Jose CA

Assignee:

NexFlash Technologies, Inc. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518528, 36518518, 36536517

Abstract:

A memory array contains memory cells designed to be erased using Fowler-Nordheim (âFNâ) tunneling through the channel area, and programmed using either channel hot electron injection (âCHEâ) or channel-initiated secondary electron injection (âCISEIâ). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

US Patent:

20100123506, May 20, 2010

Filed:

Nov 20, 2008

Appl. No.:

12/275109

Inventors:

Cung Vu - San Jose CA, US
Dung Tran - Milpitas CA, US

International Classification:

H03L 5/00

US Classification:

327333

Abstract:

Multistage signal amplification, including level translation, improves signal integrity, e.g., slew rate, complementary signal delay and duty cycle performance, by mirroring complementary output current in an output stage based on a signal developed in an input stage pull-up network. A multistage amplifier may comprise a first stage comprising a differential input circuit coupled, respectively, between first and second inputs and first and second nodes, wherein the first node is coupled to a first pull-up circuit controlled by the first node and the second node is coupled to a second pull-up circuit controlled by the second node; and a second stage comprising a complementary output circuit coupled, respectively, between first and second nodes and first and second outputs, wherein a current mirror sinks essentially the same current at the first output as is sourced at the second output and vice versa. The pull-up network may further comprise a cross-coupled pull-up circuit.

US Patent:

60207434, Feb 1, 2000

Filed:

Oct 21, 1997

Appl. No.:

8/955433

Inventors:

Larry D. Reeves - Palo Alto CA
Dung A. Tran - San Jose CA

Assignee:

Compaq Computer Corporation - Cupertino CA

International Classification:

G01N 27416

US Classification:

324434

Abstract:

A technique for detecting failed batteries while the battery is attached to one or more electronic devices and is receiving a float charge is disclosed. The float voltage minimizes the normal voltage differences between battery cells. The technique employs a ratio comparative analysis of cell voltages of a battery provided across the terminals of the battery. Application of the ratio comparative analysis in assessing the condition of a battery assumes an equal voltage drop across each battery cell such that the cells are modeled as a series of resisters with respect to the float voltage. Such equal voltage drop enables a comparative ratio analysis of the voltage across each of the two portions of the battery's cell stack to the voltage across the entire battery. The comparative ratio analysis determines a voltage threshold that identifies whether a battery has a shorted or open cell.

US Patent:

48872415, Dec 12, 1989

Filed:

Jul 31, 1986

Appl. No.:

6/891507

Inventors:

Dung Q. Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 800
G11C 700
G11C 1700
G11C 1136

US Classification:

36523006

Abstract:

An apparatus for programming an ECL PROM comprises conventional ECL row and column address circuits for selecting a particular fuse in the ECL PROM. The selection of a particular fuse in the ECL PROM generates a control signal in the address decoders corresponding thereto which enables a current drive gate and a current sink gate coupled thereto. A row program control circuit and a column program circuit are then enabled by an increase of potential applied thereto for turning on the current drive gate and the current sink gate coupled to the selected fuse. The turning on of the current drive gate and the current sink gate coupled to the selected fuse causes 50 to 10 milliamps to flow through the selected fuse, blowing the fuse.

US Patent:

50362291, Jul 30, 1991

Filed:

Jul 18, 1989

Appl. No.:

7/381566

Inventors:

Dung Q. Tran - San Jose CA

Assignee:

Gazelle Microcircuits, Inc. - Santa Clara CA

International Classification:

G06G 712
H03K 301

US Classification:

307497

Abstract:

A charge pump essentially incorporating parallel connections of low capacity charge pumps, where each low capacity charge pump is controlled by a clock signal, where the clock signal associated with a low capacity charge pump has a phase different than the other clock signals. Hence, the output of these essentially parallel connected charge pumps will have a ripple period which is a fraction of the period of any single clock signal, wherein the fraction is equal to 1/n, where n is the number of parallel low capacity charge pumps. This results in a ripple magnitude of 1/n that of charge pumps using a single clock source with identical input and output capacitance.

US Patent:

51270269, Jun 30, 1992

Filed:

Apr 5, 1990

Appl. No.:

7/505857

Inventors:

Richard J. Kelly - Santa Clara CA
Andrew C. Graham - Sunnyvale CA
Dung Q. Tran - San Jose CA

Assignee:

Gazelle Microcircuits, Inc. - Santa Clara CA

International Classification:

H04L 700

US Classification:

375106

Abstract:

In accordance with the invention, a circuit and a method for extracting a clock signal from a serial data stream are provided. A window pulse is generated such that transitions of a delayed version of the serial data stream occur near the center of the window pulse. A PUP signal and a PDN signal are generated having pulse widths indicative of the time at which transitions of the clock signal occur with respect to the window pulse. The PUP and PDN signals are used to generate a reference voltage to control the clock frequency. Window pulses may be generated in response to only positive transitions or to only negative transitions of the delayed serial data stream, or alternatively may be generated in response to both negative and positive transistions. The amount of delay introduced to the serial data stream may be selectively adjusted for different bit rates.

Address:

2415 Rinconada Dr APT 67, San Jose, CA 95125

VIN:

1HGCS12888A025333

Make:

HONDA

Model:

ACCORD CPE

Year:

2008