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Dzung T Tran

age ~57

from Austin, TX

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Also known as:
  • Dzung Thien Tran
  • Dzung P Tran
  • Thien Tran Drung
Phone and address:
2728 Cradle Rock Trl, Austin, TX 78748
(512)2821427
Related to:
Connected to:

Dzung Tran Phones & Addresses

  • 2728 Cradle Rock Trl, Austin, TX 78748 • (512)2821427
  • 4208 Arsenal St, Saint Louis, MO 63116 • (314)7725839
  • 4208A Arsenal St, Saint Louis, MO 63116
  • 3624 Bamberger Ave, Saint Louis, MO 63116 • (314)7725839
  • Stillwater, OK
  • 1952 Brown Rd, Saint Louis, MO 63114 • (314)6457144

Work

  • Position:
    Private Household Service Occupations

Medicine Doctors

Dzung Tran Photo 1

Dzung U. Tran

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Specialties:
Internal Medicine
Work:
Dzung Tran MD Internal Medicine
5052 S Jones Blvd STE 130, Las Vegas, NV 89118
(702)8760186 (phone), (702)8760608 (fax)
Education:
Medical School
St. George's University School of Medicine, St. George's, Greneda
Graduated: 1992
Procedures:
Electrocardiogram (EKG or ECG)
Skin Tags Removal
Vaccine Administration
Conditions:
Acute Bronchitis
Acute Pharyngitis
Acute Upper Respiratory Tract Infections
Angina Pectoris
Atopic Dermatitis
Languages:
English
Spanish
Vietnamese
Description:
Dr. Tran graduated from the St. George's University School of Medicine, St. George's, Greneda in 1992. He works in Las Vegas, NV and specializes in Internal Medicine. Dr. Tran is affiliated with Dignity Health St Rose Dominican- Rose De Lima and Spring Valley Hospital Medical Center.
Dzung Tran Photo 2

Dzung Vu Tran

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Specialties:
Internal Medicine
Education:
St. George's University (1993) *
U M C Of Southern Nevada (1996) *Internal Medicine

Wikipedia References

Dzung Tran Photo 3

Dzung Tran

About:
Born:

Huế , South Vietnam

Work:

Dzung Tran " Dzung Tran " is a retired Vietnamese-American soccer player who spent time in the MISL I, Western Soccer Alliance and National Professional Soccer League ( 1984-2001 )
He attended Livermore High School before transferring to San Jose High School where he graduated in 1983....

Education:

That fall, he began playing soccer at Foothill College, but Golden Gate Conference officials determined that his game with the Earthquakes counted as a professional event.

Skills & Activities:
Sport:

American soccer player • American Indoor Soccer Association player • American Professional Soccer League player • Foothill Owls men’s soccer player • Los Angeles Heat player • Major Indoor Soccer League player • Milwaukee Wave player • National Professional Soccer League player • Salt Lake Sting player • San Diego Sockers (original MISL) player • San Francisco Bay Blackhawks player • San Jose Earthquakes player • San Jose Oaks player • Western Soccer Alliance player • Football

Skill:

Professional

Preference:

Communist

Name / Title
Company / Classification
Phones & Addresses
Dzung Tran
Principal
Tran, Dzung
Nonresidential Building Operator
9104 Goodale Ave, Saint Louis, MO 63114
Dzung N. Tran
Managing
Design X-Files LLC
Dzung Tran
TRAN INVESTMENTS LLC
Dzung Tran
RT TRANSPORT LLC
Dzung Tran
TRAN INVESTMENTS, INC
Dzung Tran
Governing, Governing Person, Managing
ICQY CONSULTING, LLC
6851 Matlock Rd #111, Arlington, TX 76002
10900 Stonelake Blvd, Austin, TX 78759

Us Patents

  • Level Shifter

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  • US Patent:
    7002371, Feb 21, 2006
  • Filed:
    Dec 29, 2003
  • Appl. No.:
    10/747748
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    May Len - Cedar Park TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 19/094
  • US Classification:
    326 68, 326 81, 326119, 326121, 326 63, 327333, 327427
  • Abstract:
    A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

  • Variable Impedance Output Buffer

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  • US Patent:
    7095246, Aug 22, 2006
  • Filed:
    Aug 25, 2004
  • Appl. No.:
    10/926121
  • Inventors:
    Kase Kiyoshi - Austin TX, US
    May Len - Cedar Park TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 17/16
    H03K 19/03
    H03K 19/0175
    H03K 19/094
  • US Classification:
    326 30, 326 31, 326 32, 326 33, 326 34, 326 82, 326 83, 326 85, 326 86, 326 87
  • Abstract:
    An output buffer circuit () includes an output driver transistor (), a predriver circuit (), and a bias generator (). The predriver circuit () has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (). The bias generator () is coupled to the second terminal of the predriver circuit (), and provides a bias voltage (V) to the second terminal of the predriver circuit () for controlling the gate voltage of the output driver transistor ().

  • Latching Input Buffer Circuit With Variable Hysteresis

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  • US Patent:
    7420394, Sep 2, 2008
  • Filed:
    Nov 17, 2006
  • Appl. No.:
    11/561209
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 19/094
  • US Classification:
    326 83, 326 87
  • Abstract:
    An input buffer circuit with hysteresis includes a first stage and a second stage. The first stage includes a resistive device to provide a resistance between two nodes of the first stage. The two nodes are responsive to a signal input. The second stage includes four series-coupled transistors. A first node is coupled to the control electrodes of two of the four transistors and the second node is coupled to the control electrodes of the other two transistors. The second stage includes a signal output. In some examples, a resistance provided by the resistive device is variable and provides the buffer circuit with hysteresis.

  • Voltage Control Circuit Having A Power Switch

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  • US Patent:
    7432754, Oct 7, 2008
  • Filed:
    Jul 27, 2006
  • Appl. No.:
    11/460349
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 17/00
  • US Classification:
    327408, 327108, 327407, 327534
  • Abstract:
    A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

  • Low Voltage Circuit With Variable Substrate Bias

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  • US Patent:
    7479813, Jan 20, 2009
  • Filed:
    Jun 14, 2006
  • Appl. No.:
    11/424132
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    Dzung T. Tran - Austin TX, US
    May Len - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03B 1/00
    H03K 3/00
  • US Classification:
    327108, 326 68, 326 81, 327534, 327537, 327333
  • Abstract:
    In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

  • Performance Variation Compensating Circuit And Method

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  • US Patent:
    7508246, Mar 24, 2009
  • Filed:
    Sep 15, 2006
  • Appl. No.:
    11/532295
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03H 11/26
    H03B 1/00
    H03K 19/094
  • US Classification:
    327261, 327108, 326 30, 326 86
  • Abstract:
    A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

  • Input Buffer

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  • US Patent:
    7667492, Feb 23, 2010
  • Filed:
    Dec 21, 2007
  • Appl. No.:
    12/004617
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    May Len - Lawrenceville GA, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 19/094
  • US Classification:
    326 83, 326 87
  • Abstract:
    Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

  • Electronic Device And Method

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  • US Patent:
    7768296, Aug 3, 2010
  • Filed:
    Feb 23, 2006
  • Appl. No.:
    11/360724
  • Inventors:
    Kiyoshi Kase - Austin TX, US
    Dzung T. Tran - Austin TX, US
  • Assignee:
    Freescale Semiconductor, Inc. - Austin TX
  • International Classification:
    H03K 19/003
    H03K 17/16
  • US Classification:
    326 27, 326 17, 326 82
  • Abstract:
    A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.

License Records

Dzung Tran

License #:
45312 - Expired
Category:
Nursing Support
Issued Date:
Sep 22, 1999
Effective Date:
Sep 3, 2001
Type:
Nurse Aide

Dzung Tran

License #:
4815 - Expired
Category:
Pharmacy
Issued Date:
Aug 24, 2000
Effective Date:
Sep 16, 2005
Expiration Date:
Sep 1, 2005
Type:
Pharmacist Intern

Resumes

Dzung Tran Photo 4

Phd Candidate

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Location:
Tampa, FL
Industry:
Mechanical Or Industrial Engineering
Work:
University of South Florida
Phd Candidate
Florida State University May 2013 - Jul 2013
Undergraduate Research
Education:
Missouri University of Science and Technology 2012 - 2014
Bachelors, Bachelor of Arts, Mechanical Engineering
Skills:
Matlab
Ni Labview
Solidworks
Microsoft Office
C/C++ Stl
Microsoft Excel
Arduino
Engineering
Mechanical Engineering
Languages:
Vietnamese
Dzung Tran Photo 5

Senior Ic Design Engineer

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Location:
729 south Almaden Ave, San Jose, CA 95110
Industry:
Semiconductors
Work:
Freescale Semiconductor
Senior Ic Design Engineer
Freescale Semiconductor Jan 1997 - Jun 2009
Mixed-Signal Ic Designer
Education:
Oklahoma State University 1995 - 1996
Master of Science, Masters, Computer Engineering, Design Missouri University of Science and Technology 1991 - 1994
Bachelors, Bachelor of Science, Electrical Engineering The University of Texas at Austin
Skills:
Ic
Cmos
Mixed Signal
Integrated Circuit Design
Analog
Circuit Design
Timing Closure
Embedded Systems
Rf
Vlsi
Digital Signal Processors
Functional Verification
Low Power Design
Usb
Eda
Interests:
Boating
Collecting
Cooking
Exercise
Electronics
Traveling
Nascar
Outdoors
Home Improvement
International Traavel
Sweepstakes
Reading
Sports
Music
Travel
Movies
Fishing
Dzung Tran Photo 6

Dzung Tran

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Education:
Gateway Community College New Haven, Ct 2013 - 2014
Dzung Tran Photo 7

Research Engineer 3

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Work:

Research Engineer 3
Dzung Tran Photo 8

Dzung Tran

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Dzung Tran Photo 9

Dzung Tran

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Dzung Tran Photo 10

Dzung Tran

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Location:
United States

Facebook

Dzung Tran Photo 11

Dzung Tran Silic Valley CA

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Dzung Tran (Silicon Valley, CA)
Dzung Tran Photo 12

Dzung Tran Vietnam

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Dzung Tran (Vietnam)
Dzung Tran Photo 13

Dzung Tran Bat Rouge LA

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Dzung Tran (Baton Rouge, LA)
Dzung Tran Photo 14

Dzung Tran Australia

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Friends:
William Fong, Nicole Walter, Debbie Micairan, Sally Phan
Dzung Tran (Australia)
Dzung Tran Photo 15

Dzung Tran

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Dzung Tran Photo 16

Dzung Tran Viet

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Dzung Tran Photo 17

Dzung Tran Vu

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Dzung Tran Photo 18

Dzung Tran

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Classmates

Dzung Tran Photo 19

Dzung Tran

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Schools:
Nashua Elementary School Nashua MT 1974-1978
Community:
Larry Schmidt
Dzung Tran Photo 20

Dzung Tran

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Schools:
FORSET LAWN HIGH SCHOOL Calgary Azores 1992-1996
Community:
Walter Litke, Becky Picciano, Blair Dickey
Dzung Tran Photo 21

Dzung Tran

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Schools:
Anacapa Middle School Ventura CA 1991-1995
Community:
Mark Carlson, Lamarvie Koester
Dzung Tran Photo 22

Dzung Dzung Tran, Ventura...

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Dzung Dzung Tran 1999 graduate of Buena High School in Ventura, CA
Dzung Tran Photo 23

Dzung Tran, San diego, CA

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Dzung Tran 1983 graduate of Patrick Henry High School in San diego, CA
Dzung Tran Photo 24

Colorado School of Mines,...

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Graduates:
Tatum Mattox (1996-2000),
Dzung Tran (1978-1982),
Andrew Montano (2002-2005),
Richard Schalhamer (1988-2004)
Dzung Tran Photo 25

Bluevale High School, Wat...

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Graduates:
Dzung Tran (1989-1993),
Petra Karrenbrock (1980-1984),
Libby Asmussen (1996-2000),
Jeannie Lynham (1985-1986)
Dzung Tran Photo 26

Anacapa Middle School, Ve...

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Graduates:
Kristi Perzel (1997-1999),
Leanna Mounsey (1989-1993),
Rodriguez Gonzales (2001-2005),
Dzung Tran (1991-1995),
Dung Tran (1993-1995)

Flickr

Dzung Tran Photo 27
Dzung Tran Photo 28
Dzung Tran Photo 29
Dzung Tran Photo 30
Dzung Tran Photo 31
Dzung Tran Photo 32
Dzung Tran Photo 33
Dzung Tran Photo 34

Googleplus

Dzung Tran Photo 35

Dzung Tran

Work:
Amcal Pharmacy Northlakes - Pharmacy Assistant (2010)
Amcal Pharmacy Humpty Doo - Pharmacy Assistant (2010)
Education:
Charles Darwin University - Bachelor of Pharmacy
About:
Hi, what's your name?
Bragging Rights:
Survive everyday
Dzung Tran Photo 36

Dzung Tran

Work:
Biomedvn - Product manager (2009)
Education:
Vietnam National University of Hanoi - Biotechnology
Tagline:
A Cowboy
Dzung Tran Photo 37

Dzung Tran

Work:
Viettel Telecom - Binh Nhất (2008)
Education:
Ha Noi University Communication and Transport - IT
Tagline:
Một Vợ - Một Con - Một Khoản Nợ
Dzung Tran Photo 38

Dzung Tran

Work:
Hyundai Heavy Industries - Acc
Education:
PDU
Dzung Tran Photo 39

Dzung Tran

Work:
Vina Explorer Travel Group - Chủ tịch tập đoàn
About:
Chairman: Vina Explorer Travel Group CEO: Mekong Delta Explorer, Phu Quoc Explorer, Con Dao Explorer, Nha Trang Explorer, Da Nang Explorer & Campuchia Tour
Tagline:
Công ty du lịch quản lý điểm đến tại Việt Nam - Vina Explorer Travel Group
Bragging Rights:
Cử nhân Kinh tế đối ngoại - FTU
Dzung Tran Photo 40

Dzung Tran

Work:
TM&TVTK VD
PVFC
Dzung Tran Photo 41

Dzung Tran

Education:
Lycoming College - Computer science
Dzung Tran Photo 42

Dzung Tran

Youtube

Cy cu Da- Nhu Linh

Cy cu Da- Nhu Linh

We ,The Four Seasons Band in San Jose , California USA made this video...

  • Duration:
    5m 14s

Vietnamese-born Dzung Tran speaks about his i...

Vietnamese-born Dzung Tran speaks about his inspir...

SUBSCRIBE: LIKE:...

  • Duration:
    3m 3s

Hoa tm ngy xa

Hoa tm ngy xa

We, The Four Seasons Band in San Jose, California, own this music vide...

  • Duration:
    6m 51s

Nng chiu

Nng chiu

We, The Four Seasons Band in San Jose, California, own this music vide...

  • Duration:
    4m 49s

Cn tui no cho em, tc gi c nhc s Trnh Cng Sn....

Cn tui no cho em, tc gi c nhc s Trnh Cng Sn. Tin...

We, The Four Seasons Band in San Jose, California, own this music vide...

  • Duration:
    5m 16s

Na vng trng.

Na vng trng.

Clip gii thiu v ban nhc vn.

  • Duration:
    5m 24s

Myspace

Dzung Tran Photo 43

DZung TRan

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Locality:
SAN JOSE, California
Birthday:
1925
Dzung Tran Photo 44

Dzung Tran

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Locality:
SAN JOSE, California
Birthday:
1938
Dzung Tran Photo 45

dzung tran

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Birthday:
1947
Dzung Tran Photo 46

DZung TRan

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Birthday:
1929
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