Eddie W Lee

US Patent:

47326581, Mar 22, 1988

Filed:

Dec 3, 1986

Appl. No.:

6/937577

Inventors:

Eddie C. Lee - Bloomington MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

C23C 1434
H01L 21308
H01L 21324

US Classification:

437228

Abstract:

A substantially planar surface is provided over a silicon semiconductor device by depositing a silicate glass, heating the silicate glass so it reflows, bias sputtering a dielectric layer over the reflowed glass, depositing a photoresist over the dielectric layer and etching away the photoresist and enough of the dielectric to provide a substantially planar surface of the dielectric material. Quartz is the preferred dielectric material.

US Patent:

47174498, Jan 5, 1988

Filed:

Jul 25, 1986

Appl. No.:

6/890874

Inventors:

David G. Erie - Cottage Grove MN
Jon A. Roberts - Minnetonka MN
Eddie C. Lee - Bloomington MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 21306
B44C 122
C03C 1500
C03C 2506

US Classification:

437195

Abstract:

Disclosed is a method of fabricating an integrated circuit. A substrate comprising a semiconductor material and having a first surface is provided. A first layer of metalization interconnects is formed on the first surface. A first thin film layer comprising a dielectric barrier material is deposited over the first layer of metalization interconnects. A second thin film layer comprising a dielectric passivating material is deposited over the first thin film layer of dielectric barrier material. A via having a width greater than the width of a metalization interconnect is then plasma etched in the dielectric passivating material using a first etch gas. The dielectric barrier material is then plasma etched using a second etch gas to remove the dielectric barrier material in the area of the via. A second layer of metalization interconnects is then formed, a metalization interconnect in each of the first and second layers of metalization interconnects being connected in the via.

US Patent:

46629890, May 5, 1987

Filed:

Oct 4, 1985

Appl. No.:

6/784925

Inventors:

Daniel K. Casey - Elk River MN
Eddie C. Lee - Bloomington MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

B44C 122
C03C 1500
C03C 2506
B29C 3700

US Classification:

156655

Abstract:

An improved high efficiency metal lift-off process for removing a layer of metal at least partially covering a layer of photoresist. The method comprises forming microcracks located above the layer of photoresist in the layer of metal to be removed and providing solvent to the layer of photoresist through the microcracks.

US Patent:

47136820, Dec 15, 1987

Filed:

Dec 31, 1985

Appl. No.:

6/815426

Inventors:

David G. Erie - Cottage Grove MN
Jon A. Roberts - Minnetonka MN
Eddie C. Lee - Bloomington MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 2934

US Classification:

357 54

Abstract:

An integrated circuit comprising a substrate. The substrate comprises a semiconductor material and has a first surface. The circuit further comprises a layer of metalization interconnects over the first surface, each interconnect having a width. A first thin film layer comprising a dielectric barrier material is deposited directly onto the first layer of metalization interconnects. A second thin film layer comprising a dielectric passivating material is deposited directly onto the first thin layer of dielectric barrier material. A via is formed in the two thin film layers over a first metalization interconnect protruding into the via. The first metalization interconnect has a width less than the width of the via. A second metallization interconnect is connected to the first metalization interconnect in the via.

US Patent:

45840792, Apr 22, 1986

Filed:

Oct 11, 1983

Appl. No.:

6/540246

Inventors:

Eddie C. Lee - Bloomington MN
William H. Nunne - New Hope MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

C23C 1500

US Classification:

204192S

Abstract:

Disclosed is a method for tailoring the shape of a dielectric layer covering a step in a semiconductor device. The method comprises placing a semiconductor device comprising the step into a low pressure ionization chamber comprising a target electrode and a substrate electrode; connecting a sample of the dielectric to the target electrode; placing the semiconductor device comprising the step onto the substrate electrode; powering the target electrode and the substrate electrode with a radio frequency power having an electrical phase angle between the substrate electrode and the target electrode; and adjusting the electrical phase angle to obtain the desired shape of the dielectric layer covering the step.