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Edgardo Ariel Laber

age ~59

from Monte Sereno, CA

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Also known as:
  • Edgardo A Laber
  • Edgardo Ariel Andrea
  • Edgardo A Delaber
Related to:
Connected to:

Edgardo Laber Phones & Addresses

  • Monte Sereno, CA
  • 1134 Braemer Ct, San Jose, CA 95132
  • Santa Clara, CA
  • 16110 Viewfield Rd, Monte Sereno, CA 95030

Work

  • Company:
    Intersil
    2004
  • Position:
    Sr. design manager

Education

  • Degree:
    Master of Science, Masters
  • School / High School:
    San Jose State University
    1991 to 1993
  • Specialities:
    Electronics Engineering

Skills

Mixed Signal • Analog Circuit Design • Power Management • Cmos • Analog • Ic • Soc • Circuit Design • Asic • Low Power Design • Sensors • Silicon • Rf • Mixed Signal Ic Design • Vlsi • Lvs • Simulations • Pll • Semiconductors • Spectre • Serdes • Physical Design • Integrated Circuit Design • Semiconductor Industry • Floorplanning • Dft • Drc • Bicmos • Pcb Design • Electronics • Fpga • Static Timing Analysis • Cadence Virtuoso • Digital Signal Processors • Eda • Hardware Architecture • Cadence • Signal Integrity • Verilog • Microelectronics • Primetime • Spice • Rtl Design • Timing Closure • Technical Marketing • Tcl • Microprocessors • Power Electronics • Physical Verification • Debugging

Languages

English • Spanish

Industries

Semiconductors

Resumes

Edgardo Laber Photo 1

Senior Manager, Design Engineering, Automotive Business Unit

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Location:
Berkeley, CA
Industry:
Semiconductors
Work:
Intersil since 2004
Sr. Design Manager
Xicor 2000 - 2004
Design Manager
Micro Linear 1993 - 2000
Design Manager
Education:
San Jose State University 1991 - 1993
Master of Science, Masters, Electronics Engineering University of Buenos Aires 1985 - 1991
Skills:
Mixed Signal
Analog Circuit Design
Power Management
Cmos
Analog
Ic
Soc
Circuit Design
Asic
Low Power Design
Sensors
Silicon
Rf
Mixed Signal Ic Design
Vlsi
Lvs
Simulations
Pll
Semiconductors
Spectre
Serdes
Physical Design
Integrated Circuit Design
Semiconductor Industry
Floorplanning
Dft
Drc
Bicmos
Pcb Design
Electronics
Fpga
Static Timing Analysis
Cadence Virtuoso
Digital Signal Processors
Eda
Hardware Architecture
Cadence
Signal Integrity
Verilog
Microelectronics
Primetime
Spice
Rtl Design
Timing Closure
Technical Marketing
Tcl
Microprocessors
Power Electronics
Physical Verification
Debugging
Languages:
English
Spanish

Us Patents

  • On-Chip Ee-Prom Programming Waveform Generation

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  • US Patent:
    7158412, Jan 2, 2007
  • Filed:
    Jan 26, 2005
  • Appl. No.:
    11/044948
  • Inventors:
    Edgardo A. Laber - San Jose CA, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 16/04
  • US Classification:
    36518518, 36518911, 36518519
  • Abstract:
    Circuit methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

  • On-Chip Ee-Prom Programming Waveform Generation

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  • US Patent:
    7502264, Mar 10, 2009
  • Filed:
    Nov 30, 2006
  • Appl. No.:
    11/565039
  • Inventors:
    Edgardo A. Laber - San Jose CA, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 11/34
  • US Classification:
    36518518, 36518511, 36518519
  • Abstract:
    Circuits, methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

  • Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    7688627, Mar 30, 2010
  • Filed:
    Sep 25, 2007
  • Appl. No.:
    11/861102
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Prabhjot Singh - San Jose CA, US
    Michael D. Church - Sebastian FL, US
  • Assignee:
    Intersil Americas Inc. - Milipitas CA
  • International Classification:
    G11C 14/00
    G11C 16/04
  • US Classification:
    36518508, 36518505, 36518506, 3651851
  • Abstract:
    A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

  • Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    7903465, Mar 8, 2011
  • Filed:
    Sep 25, 2007
  • Appl. No.:
    11/861111
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Michael D. Church - Sebastian FL, US
    Yun Yue - Melbourne FL, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 16/06
    G11C 16/10
    G11C 16/12
  • US Classification:
    36518518, 36518524, 36518505
  • Abstract:
    A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

  • Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    7944745, May 17, 2011
  • Filed:
    Feb 24, 2010
  • Appl. No.:
    12/711520
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Prabhjot Singh - San Jose CA, US
    Michael D. Church - Sebastian FL, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 11/34
    G11C 16/04
  • US Classification:
    36518508, 36518506, 3651851, 36518517, 36518528
  • Abstract:
    A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

  • Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    8218370, Jul 10, 2012
  • Filed:
    Jan 24, 2011
  • Appl. No.:
    13/012368
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Michael D. Church - Canyon Lake FL, US
    Yun Yue - Melbourne FL, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 16/14
    G11C 16/10
    G11C 16/08
    G11C 16/24
    G11C 16/06
    G11C 16/04
  • US Classification:
    36518529, 36518505, 36518518, 3651851, 365184
  • Abstract:
    A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

  • Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    8315100, Nov 20, 2012
  • Filed:
    Jan 24, 2011
  • Appl. No.:
    13/012381
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Michael D. Church - Canyon Lake FL, US
    Yun Yue - Melbourne FL, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 16/06
    G11C 16/26
    G11C 16/34
    G11C 16/04
  • US Classification:
    36518518, 365184, 36518505, 36518915, 36518521, 36518523
  • Abstract:
    A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

  • Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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  • US Patent:
    8325522, Dec 4, 2012
  • Filed:
    Jan 24, 2011
  • Appl. No.:
    13/012361
  • Inventors:
    Hosam Haggag - Mountain View CA, US
    Alexander Kalnitsky - San Francisco CA, US
    Edgardo Laber - San Jose CA, US
    Michael D. Church - Canyon Lake FL, US
    Yun Yue - Melbourne FL, US
  • Assignee:
    Intersil Americas Inc. - Milpitas CA
  • International Classification:
    G11C 16/04
    G11C 16/06
  • US Classification:
    36518505, 36518518, 365184
  • Abstract:
    A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
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