Edmund William Burke

US Patent:

6898068, May 24, 2005

Filed:

Sep 24, 2003

Appl. No.:

10/669847

Inventors:

Timothy A. Rost - Plano TX, US
Edmund Burke - Dallas TX, US
Satyavolu S. Papa Rao - Garland TX, US
Rose Alyssa Keagy - Addison TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01G004/35

US Classification:

361302, 3613211, 3613214, 3613014, 361320, 361311

Abstract:

An embodiment of the invention is a capacitor comprising a bottom electrode coupled to a first interconnect of the top metal level , a capacitor dielectric , sidewalls , and a top electrode coupled to a second interconnect of the top metal level. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask to form a material stack that includes a bottom electrodes coupled to a first interconnect of the top metal level , a capacitor dielectric , and a partial top electrode. The method further includes using a second mask to form a complete top electrode coupled to a second interconnect of the top metal level.

US Patent:

6924208, Aug 2, 2005

Filed:

Apr 23, 2004

Appl. No.:

10/831471

Inventors:

Timothy A. Rost - Plano TX, US
Edmund Burke - Dallas TX, US
Satyavolu S. Papa Rao - Garland TX, US
Rose Alyssa Keagy - Addison TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/20

US Classification:

438399, 438239, 438250, 438253, 257 68, 257 71

Abstract:

An embodiment of the invention is a capacitor comprising a bottom electrode coupled to a first interconnect of the top metal level a capacitor dielectric sidewalls and a top electrode coupled to a second interconnect of the top metal level Another embodiment of the invention is a method of manufacturing a capacitor using a first mask to form a material stack that includes a bottom electrode coupled to a first interconnect of the top metal level a capacitor dielectric and a partial top electrode The method further includes using a second mask to form a complete top electrode coupled to a second interconnect of the top metal level.

US Patent:

6969880, Nov 29, 2005

Filed:

Sep 24, 2003

Appl. No.:

10/670037

Inventors:

Edmund Burke - Dallas TX, US
Benjamin P. McKee - Richardson TX, US
Frank S. Johnson - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L027/108
H01L021/20

US Classification:

257296, 257300, 257310, 257532, 438393, 438250, 438239

Abstract:

A capacitive structure (). The capacitive structure comprises a semiconductor base region () having an upper surface, a well () formed within the semiconductor base region and adjacent the upper surface, a first dielectric layer () adjacent at least a portion of the upper surface, and a polysilicon layer () adjacent the first dielectric layer. The well, the first dielectric layer, and the first polysilicon layer form a first capacitor and are aligned along a planar dimension. The capacitive structure further comprises a first conductive layer () positioned with at least a portion overlying at least a portion of the polysilicon layer, a second dielectric layer () adjacent the first conductive layer, and a second conductive layer () adjacent the second dielectric layer. The first conductive layer, the second dielectric layer, and the second conductive layer form a second capacitor and are aligned along the planar dimension.

US Patent:

7015093, Mar 21, 2006

Filed:

Oct 30, 2003

Appl. No.:

10/697139

Inventors:

Satyavolu S. Papa Rao - Garland TX, US
Timothy A. Rost - Plano TX, US
Edmund Burke - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8242

US Classification:

438250, 438396

Abstract:

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection layer () for the copper metal () of the top metal interconnect.

US Patent:

7291897, Nov 6, 2007

Filed:

Oct 30, 2003

Appl. No.:

10/696816

Inventors:

Timothy A. Rost - Plano TX, US
Edmund Burke - Dallas TX, US
Satyavolu S. Papa Rao - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/00

US Classification:

257535, 257532

Abstract:

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and may be implemented with only one additional masking layer. The decoupling capacitor () is formed on a copper interconnect line (). An aluminum cap layer () provides electrical connection to the top electrode () of the decoupling capacitor ().

US Patent:

7674682, Mar 9, 2010

Filed:

Oct 30, 2003

Appl. No.:

10/697138

Inventors:

Edmund Burke - Dallas TX, US
Satyavolu S. Papa Rao - Garland TX, US
Timothy A. Rost - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/331

US Classification:

438396, 438393, 257E2102, 257E21011

Abstract:

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection cladding () for the copper metal () of the top metal interconnect.

US Patent:

8604587, Dec 10, 2013

Filed:

Jan 19, 2010

Appl. No.:

12/689685

Inventors:

Edmund Burke - Dallas TX, US
Satyavolu Srinivas Papa Rao - Garland TX, US
Timothy Alan Rost - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/02

US Classification:

257532, 257535, 257E29345, 257E29343

Abstract:

An on-chip decoupling capacitor () and method of fabrication. The decoupling capacitor () is integrated at the top metal interconnect level () and includes surface protection cladding () for the copper metal () of the top metal interconnect.

US Patent:

20060009030, Jan 12, 2006

Filed:

Jul 7, 2005

Appl. No.:

11/175174

Inventors:

Alfred Griffin - Dallas TX, US
Edmund Burke - Dallas TX, US
Asad Haider - Plano TX, US
Kelly Taylor - Allen TX, US
Tae Kim - Dallas TX, US

International Classification:

H01L 21/4763
H01L 21/44

US Classification:

438637000, 438672000, 438644000

Abstract:

Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.