Edmund Y Cheung

US Patent:

6680738, Jan 20, 2004

Filed:

Feb 22, 2002

Appl. No.:

09/683852

Inventors:

Takatoshi Ishii - Sunnyvale CA
Edmund Cheung - Palo Alto CA
Sherwood Brannon - Mountain View CA

Assignee:

NeoMagic Corp. - Santa Clara CA

International Classification:

G06F 1210

US Classification:

345568, 345572, 345656

Abstract:

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,. eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

US Patent:

RE39963, Dec 25, 2007

Filed:

May 13, 2005

Appl. No.:

11/129758

Inventors:

Edmund Cheung - Palo Alto CA, US
Otto Sponring - Los Altos CA, US

Assignee:

Faust Communications LLC - Las Vegas NV

International Classification:

G06F 1/32

US Classification:

713322, 713501

Abstract:

An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are “resources. ” The devices that access the resources are “controllers. ” The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table.

US Patent:

7400328, Jul 15, 2008

Filed:

Feb 18, 2005

Appl. No.:

10/906409

Inventors:

Bo Ye - Cupertino CA, US
Jimmy Yang - Saratoga CA, US
Edmund Cheung - Palo Alto CA, US

Assignee:

NeoMagic Corp. - Santa Clara CA

International Classification:

G06F 13/00
G09G 5/00

US Classification:

345537, 345558, 345559, 345531, 345589, 345629

Abstract:

A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primary and secondary row indicator bits and each block-column has two column indicator bits. When the primary row indicator bit is cleared, all pixels in the block-row are fetched from a frame-buffer memory. When the primary row indicator is set, a secondary row indicator bit selects either first or second column indicator bits for reading. When the selected column indicator bit for a block-column is set, fetching of pixels from the frame buffer memory is skipped. Instead, dummy color-key pixels are generated and inserted into the pixel stream. These dummy pixels match the color key and cause video pixels to be sent to the display.

US Patent:

RE41967, Nov 30, 2010

Filed:

Jan 20, 2006

Appl. No.:

11/337221

Inventors:

Takatoshi Ishii - Sunnyvale CA, US
Edmund Cheung - Palo Alto CA, US
Sherwood Brannon - Boca Raton FL, US

International Classification:

G06F 12/10
G06F 12/06
G09G 3/37
G09G 5/00

US Classification:

345568, 345572, 345562, 345656

Abstract:

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,. eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

US Patent:

RE43235, Mar 13, 2012

Filed:

May 28, 2010

Appl. No.:

12/789856

Inventors:

Takatoshi Ishii - Sunnyvale CA, US
Edmund Cheung - Palo Alto CA, US
Sherwood Brannon - Sebastian FL, US

Assignee:

Faust Communications, LLC - Las Vegas NV

International Classification:

G06F 12/10
G06F 12/06
G09G 3/37
G09G 5/00
G09G 5/36

US Classification:

345568, 345545, 345562, 345572, 345656

Abstract:

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,. eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

US Patent:

6564329, May 13, 2003

Filed:

Mar 16, 1999

Appl. No.:

09/270312

Inventors:

Edmund Cheung - Palo Alto CA
Otto Sponring - Los Altos CA

Assignee:

Linkup Systems Corporation - San Jose CA

International Classification:

G06F 108

US Classification:

713322, 713501

Abstract:

An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are âresources. â The devices that access the resources are âcontrollers. â The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table.